Cirrus-logic CS4202 User Manual Page 9
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CS4202
DS549PP2 9
AC ’97 SERIAL PORT TIMING Standard test conditions unless otherwise noted: T
ambient
= 25° C,
AVdd = 5.0 V, DVdd = 3.3 V; C
L
= 55 pF load.
Parameter Symbol Min Typ Max Unit
RESET Timing
RESET# active low pulse width T
rst_low
1.0 - - µs
RESET# inactive to BIT_CLK start-up delay (XTL mode)
(OSC mode)
(PLL mode)
T
rst2clk
-
-
-
4.0
4.0
2.5
-
-
-
µs
µs
ms
1st SYNC active to CODEC READY ‘set’ T
sync2crd
-62.5-µs
Vdd stable to RESET# inactive T
vdd2rst#
100 - - µs
Clocks
BIT_CLK frequency F
clk
- 12.288 - MHz
BIT_CLK period T
clk_period
- 81.4 - ns
BIT_CLK output jitter (depends on XTL_IN source) - - 750 ps
BIT_CLK high pulse width T
clk_high
36 40.7 45 ns
BIT_CLK low pulse width T
clk_low
36 40.7 45 ns
SYNC frequency F
sync
- 48 - kHz
SYNC period T
sync_period
-20.8-µs
SYNC high pulse width T
sync_high
-1.3-µs
SYNC low pulse width T
sync_low
-19.5-µs
Data Setup and Hold
Output propagation delay from rising edge of BIT_CLK T
co
81012ns
Input setup time from falling edge of BIT_CLK T
isetup
10 - - ns
Input hold time from falling edge of BIT_CLK T
ihold
0--ns
Input signal rise time T
irise
2-6ns
Input signal fall time T
ifall
2-6ns
Output signal rise time (Note 4) T
orise
246ns
Output signal fall time (Note 4) T
ofall
246ns
Misc. Timing Parameters
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4) T
s2_pdown
- 0.285 1.0 µs
SYNC pulse width (PR4) Warm Reset T
sync_pr4
1.0 - - µs
SYNC inactive (PR4) to BIT_CLK start-up delay T
sync2clk
162.8 285 - ns
Setup to trailing edge of RESET# (ATE test mode) (Note 4) T
setup2rst
15 - - ns
Rising edge of RESET# to Hi-Z delay (Note 4) T
off
- - 25 ns
- Features 1
- Description 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 4
- LIST OF TABLES 5
- MIXER CHARACTERISTICS 7
- 9
- 10 DS549PP2 10
- Figure 1. Power Up Timing 10
- Figure 3. Clocks 10
- DS549PP2 11 11
- Figure 6. Test Mode 11
- 2. GENERAL DESCRIPTION 12
- 2.1 AC-Link 12
- 2.2 Control Registers 13
- 2.3 Sample Rate Converters 13
- 2.4 Mixers 13
- 2.5 Input Mux 13
- 2.6 Volume Control 13
- 14 DS549PP2 14
- 3. AC-LINK FRAME DEFINITION 15
- 20 DS549PP2 20
- 4. REGISTER INTERFACE 21
- 0000000ID8ID700ID40000 22
- Mute 0 ML5 22
- 00000SL2SL1SL000000SR2SR1SR0 26
- 000000MIXMSLPBK0000000 28
- 11111111111GP4GP3GP2GP1GP0 35
- 00000000000GS4GS3GS2GS1GS0 35
- 5. SERIAL DATA PORTS 42
- 5.1 Overview 42
- 5.2 Multi-Channel Expansion 42
- 5.3 Serial Data Formats 43
- 6. SONY/PHILIPS DIGITAL 44
- INTERFACE (S/PDIF) 44
- 7. EXCLUSIVE FUNCTIONS 44
- DS549PP2 45 45
- 8.2 Powerdown Controls 46
- + DVdd/Rload/2 47
- 9. CLOCKING 48
- 9.3 Secondary Codec Operation 48
- 22 pF 22 pF 49
- 24.576 MHz 49
- 50 DS549PP2 50
- Figure 19. Differential 1 V 50
- CD Input 50
- 10.1.4 PC Beep Input 51
- 10.1.5 Phone Input 51
- 10.2 Analog Outputs 51
- 10.2.1 Stereo Outputs 51
- 10.2.2 Mono Output 52
- 10.4 Power Supplies 52
- 10.5 Reference Design 53
- 11. GROUNDING AND LAYOUT 54
- DS549PP2 55 55
- CS4202 48-pin 56
- Package Layout 56
- Audio I/O Pins 57
- AC-Link Pins 59
- Clock and Configuration Pins 60
- Misc. Digital Interface Pins 60
- Power Supply Pins 61
- 14.REFERENCE DESIGN 64
- 15.REFERENCES 65
- 48L LQFP PACKAGE DRAWING 66
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