Cirrus-logic CS4202 User Manual Page 64
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CS4202
64 DS549PP2
14.REFERENCE DESIGN
R18
6.8K
C23 1uF
Y5V
R14 6.8K
C31
22pF
NPO
C22 1uF
Y5V
C32
22pF
NPO
J1
1
2
R11 6.8K
R4 220K
J4
4
3
5
2
1
C25
2.2uF
Y5V
C3
10uF
ELEC
+
R9 47
Y1
24.576 MHz
R5 100K
J2
1
2
3
4
C10
0.1uF
X7R
C6
10uF
ELEC
+
C30 1uF
Y5V
GND_TIE
0.050 inch
R3 100K
C29
0.1uF
X7R
J7
1
2
R20
1.5K
J6
1
2
3
4
5
6
R10
10K
R12 6.8K
J3
4
3
5
2
1
R8 47
R17 6.8K
C2
2700pF
X7R
C9 1uF
Y5V
C19 220uF
ELEC
+
U2
CS4202
LINE_OUT_R
36
MONO_OUT
37
AVdd2
38
HP_OUT_L
39
GPIO1/SDOUT
44
HP_OUT_R
41
AVss2
42
GPIO0/LRCLK
43
HP_OUT_C
40
GPIO4/SDO2
34
GPIO3
33
GPIO2
32
HPCFG
31
DVdd1
1
XTL_IN
2
XTL_OUT
3
DVss1
4
SDATA_OUT
5
BIT_CLK
6
DVss2
7
SDATA_IN
8
SYNC
10
DVdd2
9
RESET#
11
PC_BEEP
12
PHONE
13
AUX_L
14
AUX_R
15
VIDEO_L
16
VIDEO_R
17
CD_L
18
CD_C
19
CD_R
20
MIC1
21
MIC2
22
LINE_IN_L
23
LINE_IN_R
24
AVdd1
25
AVss1
26
REFFLT
27
Vrefout
28
AFLT1
29
AFLT2
30
SPDIF_OUT
48
EAPD/SCLK
47
ID1#
46
ID0#
45
LINE_OUT_L
35
C8 1uF
Y5V
R2
4.7K
R1 47K
C14 1uF
Y5V
R7 100K
C11
0.1uF
X7R
C26
0.1uF
X7R
C20 220uF
ELEC
+
C15 1uF
Y5V
U1 MC78M05ACDT
OUT
3
GND
2
IN
1
J8
4
3
5
2
1
C28
1000pF
NPO
C5
0.1uF
X7R
R16 6.8K
C27
1000pF
NPO
J5
6
2
3
1
7
C16 1000pF
NPO
R13 10K
R15 10K
C18 1uF
Y5V
R21 2.2K
C17 1000pF
NPO
C13
0.1uF
X7R
C21 1uF
Y5V
C33
10uF
ELEC
+
R6 220K
C4
0.1uF
X7R
C24
NO POP
R19
6.8K
C12
0.1uF
X7R
C7 1uF
Y5V
C1 0.1uF
X7R
RESET#
SDATAOUT
SDATAIN0
BITCLK
SYNC
HP SENSE
AGND AGND
AGND
DGND
AGND
AGND
DGND
DGND
AGND
+3.3VD
DGND DGND
+5VD
AGND
AGND
DGND AGND
AGND
+5VA
DGND AGND
AGND
DGND
AGNDAGND
+5VA+12V
DGND
+3.3VD
DGND AGND
BEEP IN
CD IN
MIC IN
LINE IN
HEADPHONE
JACK
S/PDIF OUT
Tie at one
point only
under the codec
(50 PPM)
PHONE IN
LINE OUT
JACK
PCI Audio
Controller
or ICH
Controller
AC LINK
For 2 channel
configuration
GPIO3 (pin 33)
is tied to
3.3V.
2.2uF capacitor can
be replaced by two
1uF capacitors.
Figure 28. CS4202 Reference Design
- Features 1
- Description 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 4
- LIST OF TABLES 5
- MIXER CHARACTERISTICS 7
- 9
- 10 DS549PP2 10
- Figure 1. Power Up Timing 10
- Figure 3. Clocks 10
- DS549PP2 11 11
- Figure 6. Test Mode 11
- 2. GENERAL DESCRIPTION 12
- 2.1 AC-Link 12
- 2.2 Control Registers 13
- 2.3 Sample Rate Converters 13
- 2.4 Mixers 13
- 2.5 Input Mux 13
- 2.6 Volume Control 13
- 14 DS549PP2 14
- 3. AC-LINK FRAME DEFINITION 15
- 20 DS549PP2 20
- 4. REGISTER INTERFACE 21
- 0000000ID8ID700ID40000 22
- Mute 0 ML5 22
- 00000SL2SL1SL000000SR2SR1SR0 26
- 000000MIXMSLPBK0000000 28
- 11111111111GP4GP3GP2GP1GP0 35
- 00000000000GS4GS3GS2GS1GS0 35
- 5. SERIAL DATA PORTS 42
- 5.1 Overview 42
- 5.2 Multi-Channel Expansion 42
- 5.3 Serial Data Formats 43
- 6. SONY/PHILIPS DIGITAL 44
- INTERFACE (S/PDIF) 44
- 7. EXCLUSIVE FUNCTIONS 44
- DS549PP2 45 45
- 8.2 Powerdown Controls 46
- + DVdd/Rload/2 47
- 9. CLOCKING 48
- 9.3 Secondary Codec Operation 48
- 22 pF 22 pF 49
- 24.576 MHz 49
- 50 DS549PP2 50
- Figure 19. Differential 1 V 50
- CD Input 50
- 10.1.4 PC Beep Input 51
- 10.1.5 Phone Input 51
- 10.2 Analog Outputs 51
- 10.2.1 Stereo Outputs 51
- 10.2.2 Mono Output 52
- 10.4 Power Supplies 52
- 10.5 Reference Design 53
- 11. GROUNDING AND LAYOUT 54
- DS549PP2 55 55
- CS4202 48-pin 56
- Package Layout 56
- Audio I/O Pins 57
- AC-Link Pins 59
- Clock and Configuration Pins 60
- Misc. Digital Interface Pins 60
- Power Supply Pins 61
- 14.REFERENCE DESIGN 64
- 15.REFERENCES 65
- 48L LQFP PACKAGE DRAWING 66
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