Cirrus-logic CS42426 User Manual

Copyright  Cirrus Logic, Inc. 2014 (All Rights Reserved)http://www.cirrus.com114 dB, 192-kHz 6-Ch CODEC with PLLFeatures Six 24-bit D/A, two 24-bit

10 DS604F2CS42426D/A DIGITAL FILTER CHARACTERISTICS Notes:9. Response is clock dependent and will scale with Fs. Note that the response plots (Fig

DS604F2 11CS42426SWITCHING CHARACTERISTICS(TA = -10 to +70° C; VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS

12 DS604F2CS42426SWITCHING CHARACTERISTICS - CONTROL PORT - I²C™ FORMAT(TA = -10 to +70° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: L

DS604F2 13CS42426SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT (TA = -10 to +70° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs:

14 DS604F2CS42426DC ELECTRICAL CHARACTERISTICS(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)Notes:22. Cu

DS604F2 15CS42426DIGITAL INTERFACE CHARACTERISTICS(TA = +25° C)Notes:26. Serial Port signals include: RMCK, OMCK, ADC_SCLK, ADC_LRCK, DAC_SCLK, DAC_LR

16 DS604F2CS424262. PIN DESCRIPTIONS Pin Name # Pin DescriptionDAC_SDIN1DAC_SDIN2DAC_SDIN316463DAC Serial Audio Data Input (Input) -

DS604F2 17CS42426RST12Reset (Input) - The device enters a low power mode and all internal registers are reset to their default settings when low.AINR-

18 DS604F2CS424263. TYPICAL CONNECTION DIAGRAMS VLSAOUTA1+100 µF0.1 µF++1718VQFILT+36370.1 µF4.7 µF0.1 µF+3.3 Vto +5.0 V53Analog Output Buffer 2and

DS604F2 19CS42426VLSVDAOUTA1+240.1 µF+10 µF100 µF0.1 µF++1718VQFILT+36370.1 µF4.7 µFVA+10 µF0.1 µF5153AOUTA1-AOUTB1+3534AOUTB1-AOUTA2+3233AOUTA2-AOUTB

2 DS604F2CS42426TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

20 DS604F2CS424264. APPLICATIONS4.1 OverviewThe CS42426 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital con-ve

DS604F2 21CS424264.2.2 High-Pass Filter and DC Offset CalibrationThe high-pass filter continuously subtracts a measure of the DC offset from the outpu

22 DS604F2CS424264.3.3 Digital Volume and Mute ControlEach DAC’s output level is controlled via the Volume Control registers operating over the range

DS604F2 23CS424264.4 Clock GenerationThe clock generation for the CS42426 is shown in the figure below. The internal MCLK is derived from theoutput of

24 DS604F2CS424264.4.2 OMCK System Clock ModeA special clock-switching mode is available that allows the clock that is input through the OMCK pin to b

DS604F2 25CS42426When the device is clocked from OMCK, the frequency of OMCK must be at least twice the frequency ofthe fastest Slave Mode, SCLK. For

26 DS604F2CS42426 Serial Inputs / OutputsDAC_SDIN1 left channel right channel

DS604F2 27CS424264.5.2 Serial Audio Interface FormatsThe DAC_SP and ADC_SP digital audio serial ports support five formats with varying bit depths fro

28 DS604F2CS42426 Left ChannelRight ChannelDAC_SDINxADC_SDOUT+3 +2 +1+5 +4-1-2 -3 -4 -5+3 +2 +1+5 +4-

DS604F2 29CS42426DAC_LRCKADC_LRCKDAC_SCLKADC_SCLKLSBMSB20 clks64 clks 64 clksLSBMSB LSBMSB LSBMSB LSBMSB LSBMSB MSBDAC1 DAC3 DAC5 DAC2 DAC4 DAC620 clk

DS604F2 3CS424266.7 Clock Control (address 06h) ...

30 DS604F2CS424264.5.3 ADCIN1/ADCIN2 Serial Data FormatThe two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, sup

DS604F2 31CS424264.5.4 One-Line Mode (OLM) Configurations4.5.4.1 OLM Config #1One-Line Mode Configuration #1 can support up to 6 channels of DAC data,

32 DS604F2CS424264.5.4.2 OLM Config #2This configuration will support up to 6 channels of DAC data or 6 channels of ADC data and will handle upto 20-b

DS604F2 33CS424264.5.4.3 OLM Config #3This configuration will support up to 6 channels of DAC data and 6 channels of ADC data. OLM Config #3will handl

34 DS604F2CS424264.5.4.4 OLM Config #4This One-Line Mode configuration can support up to 6 channels of DAC data on 2 DAC_SDIN pins and 2channels of AD

DS604F2 35CS424264.6 Control Port Description and TimingThe control port is used to access the registers, allowing the CS42426 to be configured for th

36 DS604F2CS424264.6.2 I²C ModeIn I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.There is no C

DS604F2 37CS42426Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shownin Figure 23, the write operat

38 DS604F2CS424264.8 Reset and Power-UpReliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks andconfig

DS604F2 39CS424265. REGISTER QUICK REFERENCEAddr Function 7 6 5 4 3 2 1 001hIDChip_ID3 Chip_ID2 Chip_ID1 Chip_ID0 Rev_ID3 Rev_ID2 Rev_ID1 Rev_ID0page

4 DS604F2CS42426Figure 17. OLM Configuration #1 ...

40 DS604F2CS4242613hVol. Control A3A3_VOL7 A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3_VOL2 A3_VOL1 A3_VOL0page 53default0 0 00000 014hVol. Control B3B3_VOL7 B

DS604F2 41CS4242623hInterrupt Mode LSBUNLOCK0 Reserved Reserved Reserved Reserved Reserved OF0 Reservedpage 57default0 0 00000 024h-27hReservedReserve

42 DS604F2CS424266. REGISTER DESCRIPTIONAll registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, Clock Sta

DS604F2 43CS424266.3 Power Control (address 02h)6.3.1 POWER DOWN PLL (PDN_PLL)Default = 0Function:When enabled, the PLL is held in a reset state. It i

44 DS604F2CS424266.4.2 ADC FUNCTIONAL MODE (ADC_FMX)Default = 0000 - Single-Speed Mode (4 to 50 kHz sample rates)01 - Double-Speed Mode (50 to 100 kHz

DS604F2 45CS424266.5 Interface Formats (address 04h)6.5.1 DIGITAL INTERFACE FORMAT (DIFX)Default = 01Function:These bits select the digital interface

46 DS604F2CS424266.5.4 CODEC RIGHT-JUSTIFIED BITS (CODEC_RJ16)Default = 0Function:This bit determines how many bits to use during Right-Justified Mode

DS604F2 47CS424266.6.4 INTERPOLATION FILTER SELECT (FILT_SEL)Default = 0Function:This feature allows the user to select whether the DAC interpolation

48 DS604F2CS424266.7 Clock Control (address 06h)6.7.1 RMCK DIVIDE (RMCK_DIVX)Default = 00Function:Divides/multiplies the internal MCLK, either from th

DS604F2 49CS424266.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX)Default = 00Function:These two bits, along with the UNLOCK bit in register “Interrupt Stat

DS604F2 5CS42426LIST OF TABLESTable 1. Common OMCK Clock Frequencies ...

50 DS604F2CS424266.9 Clock Status (address 08h) (Read Only)6.9.1 SYSTEM CLOCK SELECTION (ACTIVE_CLK)Default = x0 - Output of PLL1 - OMCKFunction:This

DS604F2 51CS424266.10 Volume Transition Control (address 0Dh)6.10.1 SINGLE VOLUME CONTROL (SNGVOL)Default = 0Function:The individual channel volume le

52 DS604F2CS424266.10.3 AUTO-MUTE (AMUTE)Default = 10 - Disabled1 - EnabledFunction:The digital-to-analog converters of the CS42426 will mute the out

DS604F2 53CS424266.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) 6.12.1 VOLUME CONTROL (XX_VOL)Default = 0Function:The Digital Volu

54 DS604F2CS424266.14.2 ATAPI CHANNEL-MIXING AND MUTING (PX_ATAPIX) Default = 01001Function:The CS42426 implements the channel-mixing functions of the

DS604F2 55CS424266.15 ADC Left Channel Gain (address 1Ch)6.15.1 ADC LEFT CHANNEL GAIN (LGAINX)Default = 00hFunction:The level of the left analog chann

56 DS604F2CS424266.17.2 DE-EMPHASIS SELECT BITS (DE-EMPHX)Default = 0000 - Reserved01 - De-Emphasis for 32 kHz sample rate.10 - De-Emphasis for 44.1 k

DS604F2 57CS424266.19 Interrupt Mask (address 21h)Default = 00000000Function:The bits of this register serve as a mask for the interrupt sources found

58 DS604F2CS424266.21.2 CHANNEL MUTES SELECT (M_AOUTXX)Default = 11110 - Channel mute is not mapped to the MUTEC pin1 - Channel mute is mapped to the

DS604F2 59CS424266.22.3 FUNCTIONAL CONTROL (FUNCTIONX)Default = 00000Function:Mute Mode - If the pin is configured as a dedicated mute pin, the functi

6 DS604F2CS424261. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Cond

60 DS604F2CS424267. PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over th

DS604F2 61CS424268. APPENDIX A: EXTERNAL FILTERS8.1 ADC Input FilterThe analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). Th

62 DS604F2CS424269. APPENDIX B: PLL FILTER9.1 External Filter Components9.1.1 GeneralThe PLL behavior is affected by the external filter component val

DS604F2 63CS424269.1.3 Circuit Board LayoutBoard layout and capacitor choice affect each other and determine the performance of the PLL. Figure26 illu

64 DS604F2CS4242610.APPENDIX C: ADC FILTER PLOTS -140-130-120-110-100-90-80-70-60-50-40-30-20-1000.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0Frequency

DS604F2 65CS42426 -10-9-8-7-6-5-4-3-2-100.40 0.43 0.45 0.48 0.50 0.53 0.55Frequency (normalized to Fs)Amplitude (dB) -0.10-0.08-0.05-0.030.

66 DS604F2CS4242611.APPENDIX D: DAC FILTER PLOTS0.4 0.5 0.6 0.7 0.8 0.9 1120100806040200Frequency(normalized to Fs)Amplitude (dB)0.4 0.42 0.44 0.46 0.

DS604F2 67CS424260 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.50.020.0150.010.00500.0050.010.0150.02Frequency(normalized to Fs)Amplitude (dB)0.45 0.46

68 DS604F2CS424260.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1120100806040200Frequency(normalized to Fs)Amplitude (dB)0.2 0.3 0.4 0.5 0.6 0.7 0.8120100806040200Fr

DS604F2 69CS424260.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55109876543210Frequency(normalized to Fs)Amplitude (dB)0 0.05 0.1 0.15 0.2 0.250.2

DS604F2 7CS42426ANALOG INPUT CHARACTERISTICS(TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Measurement

70 DS604F2CS4242612.PACKAGE DIMENSIONS THERMAL CHARACTERISTICSINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.55 0.063 --- 1.40 1.60A1 0.002 0.

DS604F2 71CS4242613.ORDERING INFORMATION14.REFERENCES1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997.http://www.cirrus.com

72 DS604F2CS4242615.REVISION HISTORY Release Date ChangesF1 November 2005 Final Release • Added Revision History table on page 71. • Updated registers

8 DS604F2CS42426A/D DIGITAL FILTER CHARACTERISTICS Notes:5. The filter frequency response scales precisely with Fs.6. Response shown is for Fs equal

DS604F2 9CS42426ANALOG OUTPUT CHARACTERISTICS(TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measurement