Cirrus-logic CS4202 User Manual download pdf (Page 39)

CS4202

DS549PP2 39

4.25 Serial Port Control Register (Index 6Ah)

SDEN Serial Data Output Enable. The SDEN bit enables transmission of serial data on the SDOUT

pin. The SDEN bit routes the left and right channel data from the AC ’97 controller to the serial

data port. The actual data routed to the serial data port are controlled through the DSA[1:0]

configuration in the Extended Audio ID Register (Index 28h). SDEN also functions as a mas-

ter control for the second serial data output port and the serial clock. Setting this bit also dis-

ables the GPIO[1:0] pins and clears the GC[1:0] bits in the GPIO Pin Configuration Register

(Index 4Ch). Clearing this bit re-enables the GPIO[1:0] pins and sets the GC[1:0] bits.

SDO2 Serial Data Output 2 Enable. The SDO2 bit enables transmission of serial data on the

GPIO4/SDO2 pin. The SDO2 bit routes the left and right channel data from the AC ’97 con-

troller to the second serial data port. The actual slots routed to the second serial data port are

controlled through the DSA[1:0] configuration in the Extended Audio ID Register (Index 28h).

This bit can only be ‘set’ if the SDEN bit is ‘1’ and will be ‘cleared’ automatically if SDEN re-

turns to ‘0’. Setting this bit also disables the GPIO4 pin and clears the GC4 bit in the GPIO

Pin Configuration Register (Index 4Ch). Clearing this bit re-enables the GPIO4 pin and sets

the GC4 bit.

SDSC Serial Clock Enable. The SDSC bit enables transmission of a serial clock on the EAPD/SCLK

pin. Serial data can be routed to DACs that support internal SCLK mode without transmitting

a serial clock. For DACs that only support external SCLK mode, transmission of a serial clock

is required and this bit must be set to ‘1’. This bit can only be set if the SDEN bit is ‘1’ and will

be cleared automatically if SDEN returns to ‘0’. Furthermore, the SDSC bit can only be ‘set’

if the EAPD bit in the Powerdown Control/Status Register (Index 26h) is ‘0’. If the SDEN bit

is ‘0’ or the EAPD bit is ‘1’, SDSC is a read-only bit and always returns ‘0’.

SDF[1:0] Serial Data Format. The SDF[1:0] bits control the format of the serial data transmitted on the

two output ports. All ports will use the same format. See Table 12 for available formats.

Default 0000h

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

SDEN00000000000SDO2SDSCSDF1SDF0

SDF1 SDF0 Serial Data Format

00 I

0 1 Left Justified

1 0 Right Justified, 20-bit data

1 1 Right Justified, 16-bit data

Table 12. Serial Data Format Selection

1 2 ... 34 35 36 37 38 39 40 41 42 43 44 ... 65 66

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Cirrus-logic CS4202 User Manual Page 39