Cirrus-logic CS4202 User Manual download pdf (Page 60)

CS4202

60 DS549PP2

Clock and Configuration Pins

XTL_IN - Crystal Input / Clock Input, Pin 2

This pin requires either a 24.576 MHz crystal, with the other pin attached to XTL_OUT, or an external

CMOS clock. XTL_IN must have a crystal or clock source attached for proper operation except when

operating in secondary codec mode. The crystal frequency must be 24.576 MHz and designed for

fundamental mode, parallel resonance operation. If an external CMOS clock is used to drive this pin, it

must run at one of these acceptable frequencies: 14.31818, 24.576, 27, or 48 MHz. When configured as

a secondary codec, all timing is derived from the BIT_CLK input signal and this pin should be left

floating. See Section 9, Clocking, for additional details.

XTL_OUT - Crystal Output / PLL Loop Filter, Pin 3

This pin is used for a crystal placed between this pin and XLT_IN. If an external 24.576 MHz clock is

used on XTL_IN, this pin must be left floating with no traces or components connected to it. If one of

the other acceptable clocks is used on XTL_IN, this pin must be connected to a loop filter circuit. See

Section 9, Clocking, for additional details.

ID1#, ID0# - Codec ID, Inputs, Pins 45 and 46

These pins select the Codec ID for the CS4202, as well as determine the rate of the incoming clock in

PLL mode. They are only sampled after the rising edge of RESET#. These pins are internally pulled up

to the digital supply voltage and should be left floating for logic ‘0’ or tied to digital ground for logic ‘1’.

Misc. Digital Interface Pins

SPDIF_OUT - Sony/Philips Digital Interface, Output, Pin 48

This pin generates the S/PDIF digital output from the CS4202 when the SPDIF bit in the Extended

Audio Status/Control Register (Index 2Ah) is ‘set’. This output may be used to directly drive a resistive

divider and coupling transformer to an RCA-type connector for use with consumer audio equipment.

When this function is not being used this output is driven to a logic ‘0’.

EAPD/SCLK - External Amplifier Powerdown / Serial Clock, Output, Pin 47

This pin is used to control the powerdown state of an audio amplifier external to the CS4202. The

output is controlled by the EAPD bit in the Powerdown Ctrl/Stat Register (Index 26h). It is driven as a

normal CMOS output and defaults low (‘0’) upon power-up. This pin also provides the serial clock for

both serial data ports when the SDSC bit in the Serial Port Control Register (Index 6Ah) is ‘set’.

GPIO0/LRCLK - General Purpose I/O / Left-Right Clock, Input/Output, Pin 43

This pin is a general purpose I/O pin that can be used to interface with various external circuitry. When

configured as an input, it functions as a Schmitt triggered input with 350 mV hysteresis at 5 V and

220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output

(4 mA drive) or as an open drain output. This pin also provides the L/R clock for both serial data ports

when the SDEN bit in the Serial Port Control Register (Index 6Ah) is ‘set’. This pin powers up in the

high impedance state for backward compatibility.

GPIO1/SDOUT - General Purpose I/O / Serial Data Output, Input/Output, Pin 44

This pin is a general purpose I/O pin that can be used to interface with various external circuitry. When

configured as an input, it functions as a Schmitt triggered input with 350 mV hysteresis at 5 V and

220 mV hysteresis at 3.3 V. When configured as an output, it can function as a normal CMOS output

(4 mA drive) or as an open drain output. This pin also provides the serial data for the first serial data

port when the SDEN bit in the Serial Port Control Register (Index 6Ah) is ‘set’. This pin powers up in

the high impedance state for backward compatibility.

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Cirrus-logic CS4202 User Manual Page 60

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