Cirrus-logic CS8406 User Manual download pdf (Page 6)

6 DS580F6

CS8406

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

(Inputs: Logic 0 = 0 V, Logic 1 = VL; C

= 20 pF)

Notes:

5. The active edge of ISCLK is programmable in Software Mode.

6. The polarity of ILRCK is programmable in Software Mode.

7. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed.

8. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.

Parameter Symbol Min Typ Max Units

SDIN Setup Time Before ISCLK Active Edge (Note 5) t

10 - - ns

SDIN Hold Time After ISCLK Active Edge (Note 5) t

8--ns

Master Mode

OMCK to ISCLK active edge delay (Note 5) t

smd

0-17ns

OMCK to ILRCK delay (Note 6) t

lmd

0-16ns

ISCLK and ILRCK Duty Cycle - 50 - %

Slave Mode

ISCLK Period t

sckw

36 - - ns

ISCLK Input Low Width t

sckl

14.4 - - ns

ISCLK Input High Width t

sckh

14.4 - - ns

ISCLK Active Edge to ILRCK Edge (Note 7) t

lrckd

10 - - ns

ILRCK Edge Setup Before ISCLK Active Edge (Note 8) t

lrcks

10 - - ns

ISCLK

ILRCK

(output)

OMCK

(input)

smd

lmd

sckh

sckl

sckw

(input)

SDIN

lrcks

lrckd

ISCLK

ILRCK

Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing

1 2 3 4 5 6 7 8 9 10 11 ... 38 39

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