Cirrus-logic CS8406 User Manual

Copyright  Cirrus Logic, Inc. 2012(All Rights Reserved)http://www.cirrus.com192 kHz Digital Audio Interface TransmitterFeatures Complete EIAJ CP1201

10 DS580F6CS8406CS8406+3.3 V or +5.0 VGNDILRCKISCLKSDINHardwareControlAPMSTCBLDRSTSFMT0VD VLTXP0.1 FSerialAudioSourceClock Sourceand ControlOMCKSFMT1

DS580F6 11CS84063. GENERAL DESCRIPTIONThe CS8406 is a monolithic CMOS device which encodes a nd transmits audio data according to the AES3,IEC60958,

12 DS580F6CS84064. THREE-WIRE SERIAL INPUT AUDIO PORTA 3-wire serial audio input port is provided. The interface format can be adjusted to suit the at

DS580F6 13CS84065. AES3 TRANSMITTERThe CS8406 includes an AES3 digital audio transmitter. A comprehensive buffering scheme provides write accessto the

14 DS580F6CS8406a) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well as a newchannel status block star

DS580F6 15CS8406U[0] U[2]Data [4] Data [5] Data [6] Data [7] Data [8]Data [0]* Data [2]* Data [4]*Z Y X* Assume MMTLR = 0Data [1]* Data [3]* Data [5]*

16 DS580F6CS84066. CONTROL PORT DESCRIPTIONThe control port is used to access the registers, allowing the CS8406 to be configured for the desired oper

DS580F6 17CS84066.2 I²C ModeIn I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. Thereis no CS p

18 DS580F6CS84067. CONTROL PORT REGISTER SUMMARYNote: Reserved registers must not be written to during normal operation. Some reserved registers are u

DS580F6 19CS84068. CONTROL PORT REGISTER BIT DEFINITIONS8.1 Memory Address Pointer (MAP)Not a registerMAP[6:0] - Memory Address Pointer. Will automati

2 DS580F6CS8406TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

20 DS580F6CS8406MMTCS - Select A or B channel status data to transmit in Mono ModeDefault = ‘0’0 - Use channel A CS data for the A subframe and use ch

DS580F6 21CS8406Default = ‘00’00 - OMCK frequency is 256*Fs01 - OMCK frequency is 384*Fs10 - OMCK frequency is 512*Fs11 - OMCK frequency is 128*Fs8.6

22 DS580F6CS84068.7 Interrupt 1 Status (07h) (Read Only)For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at

DS580F6 23CS84068.10 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)The two Interrupt Mode registers form a 2-bit code for each Interrupt Re

24 DS580F6CS8406Note: There are separate complete buffers for the Channel Status and User bits. This control bit deter-mines which buffer appears in t

DS580F6 25CS84069. PIN DESCRIPTION - SOFTWARE MODE VD 6 Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V.VL 23 Logic

26 DS580F6CS8406SDA/CDOUT 1Serial Control Data I/O (I²C Mode) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data line. SDA is

DS580F6 27CS840610.HARDWARE MODEThe CS8406 has a Hardware Mode that allows the use of the device without a microcontroller. Hardware Mode isselected b

28 DS580F6CS8406The channel status block pin (TCBL) may be an input or an output, determined by the state of the TCBLDpin. 10.2 Serial Audio PortThe

DS580F6 29CS840611.PIN DESCRIPTION - HARDWARE MODEVD 6 Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V.VL 23 Logic Power

DS580F6 3CS840615. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS ... 3515.1 AES3 Transmitter External Components ..

30 DS580F6CS8406SFMT0 SFMT145Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See Table 3 on page 28.APMS 10Seri

DS580F6 31CS840612.APPLICATIONS12.1 Reset, Power Down and Start-Up When RST is low, the CS8406 enters a low power mode and all internal states are res

32 DS580F6CS840613.PACKAGE DIMENSIONS INCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA 0.093 0.098 0.104 2.35 2.50 2.65A1 0.004 0.008 0.012 0.10 0.20 0.

DS580F6 33CS8406Notes:1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include moldmismatch and are measured

34 DS580F6CS840614.ORDERING INFORMATIONProduct Description Pb-Free Package Grade Temp Range Container Order#CS8406192 kHz Digital Audio TransmitterYES

DS580F6 35CS840615.APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS This section details the external components required to interface

36 DS580F6CS840616.APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENTThe CS8406 has a comprehensive channel status (C) and user (U) data buffe

DS580F6 37CS8406troller. This is also true if the channel status data is entered serially through the COPY/C pin when the partis in Hardware Mode.16.1

38 DS580F6CS840616.1.3.2 Two-Byte ModeThere are those applications in which the A and B channel status blocks will not be the same, and the useris int

DS580F6 39CS840617.REVISION HISTORY Release Date ChangesF3 July 2005-Updated Packaging Information to include Lead Free devices and updated “Table of

4 DS580F6CS84061. CHARACTERISTICS AND SPECIFICATIONS(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Condit

DS580F6 5CS8406DIGITAL INPUT CHARACTERISTICSDIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to 0 V.) TRANSMITTER CHARACTERISTIC

6 DS580F6CS8406SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Notes:5. The active edge of ISCLK is p

DS580F6 7CS8406SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Notes:9. If Fs is lower than 51.8

8 DS580F6CS8406SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) 13. Data must be held for suffici

DS580F6 9CS84062. TYPICAL CONNECTION DIAGRAMS CS8406+3.3 V or +5.0 VGNDRXPILRCKISCLKSDINAES3 /S/PDIFSourceMicrocontrollerSCL / CCLKSDA / CDOUTRSTAD1 /