Cirrus-logic CS53L21 User Manual Page 44
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44 DS700PP1
CS53L21
ADC I²S or Left-Justified (ADC_I²S/LJ)
Default: 0
0 - Left-Justified
1 - I²S
Function:
Selects either the I²S or Left-Justified digital interface format for the data on SDOUT. The required relation-
ship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and
the options are detailed in this section “Digital Interface Formats” on page 31.
Digital Mix (DIGMIX)
Default: 0
Function:
Routes the ADC outputs to the serial port SDOUT pin. DIGMIX selects either “raw” ADC data or SPE pro-
cessed ADC data to SDOUT. Note: If DIGMIX = 1, SPE_ENABLE must be 1 for the SPE to be functional.
Microphone Mix (MICMIX)
Default: 0
0 - Disabled; No Mix: Left/Right Channel to ADC serial port, SDOUT.
1 - Enabled; Mix: Differential mix ((A-B)/2)to ADC serial port, SDOUT.
Function:
Selects between the ADC stereo mix or a differential mix of analog inputs A and B.
6.5 MIC Control (Address 05h)
ADC Single Volume Control (ADC_SNGVOL)
Default: 0
0 - Disabled
1 - Enabled
Function:
The individual PGA Volume (PGAx_VOLx) and ADC channel attenuation (ADCx_ATTx) levels as well as
the ALC A and B enable (ALC_ENx) are independently controlled by their respective control registers when
this function is disabled. When enabled, the volume on both channels is determined by the ADCA Attenuator
Control register, or the PGAA Control register, and the ADCB Attenuator and PGAB Control registers are
ignored. The ALC enable control for channel B is controlled by the ALC A enable when the ADC_SNGVOL
bit is enabled and the ALC_ENB control register is ignored.
DIGMIX SPE_ENABLE Mix Selected
0 x ADC data to ADC serial port, SDOUT data.
1
0 Reserved
1 SPE Processed ADC data to ADC serial port, SDOUT data.
76543210
ADC_SNGVOL ADCB_DBOOST ADCA_DBOOST MICBIAS_SEL MICBIAS_LVL1 MICBIAS_LVL0 MICB_BOOST MICA_BOOST
- FEATURES 1
- SYSTEM FEATURES 1
- ™ Control) 1
- APPLICATIONS 2
- GENERAL DESCRIPTION 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 6 DS700PP1 6
- 6
- Pin Name # Pin Description 6
- DS700PP1 7 7
- DS700PP1 9 9
- 10 DS700PP1 10
- ABSOLUTE MAXIMUM RATINGS 11
- SDOUT Code with HPF On 12
- Repeated 16
- = 100 μA) 18
- (Note 14) 18
- = -100 μA) 18
- POWER CONSUMPTION 19
- 4. APPLICATIONS 20
- 4.2 Hardware Mode 21
- Software 22
- Controls: 22
- 4.3.3 Digital Routing 23
- 4.3.4 Differential Inputs 23
- 24 DS700PP1 24
- 4.3.6 MIC & PGA Gain 25
- ADCx_ATT[7:0] and 26
- PGAx_VOL[4:0] volume 26
- ALCx is enabled 26
- 4.3.8 Noise Gate 27
- 4.4 Signal Processing Engine 28
- 4.4.1 Volume Controls 28
- 4.4.2 Mono Channel Mixer 28
- 4.5 Serial Port Clocking 29
- 4.5.1 Slave 30
- 4.5.2 Master 30
- 4.6 Digital Interface Formats 31
- 4.7 Initialization 32
- 4.10 Software Mode 34
- 4.10.1 SPI Control 34
- 4.10.2 I²C Control 34
- 4 5 6 7 24 25 35
- 4.10.3.1 Map Increment (INCR) 36
- 5. REGISTER QUICK REFERENCE 37
- 38 DS700PP1 38
- DS700PP1 39 39
- 6. REGISTER DESCRIPTION 40
- 76543210 41
- Reserved M/S 43
- 6.5 MIC Control (Address 05h) 44
- 6.6 ADC Control (Address 06h) 45
- AINx_MUX[1:0] 47
- PDN_PGAx 47
- 6.8 SPE Control (Address 09h) 48
- 7. ANALOG PERFORMANCE PLOTS 56
- 8.1 Auto Detect Enabled 57
- 8.2 Auto Detect Disabled 58
- 9. PCB LAYOUT CONSIDERATIONS 59
- 10.DIGITAL FILTERS 60
- 11.PARAMETER DEFINITIONS 61
- 12.PACKAGE DIMENSIONS 62
- THERMAL CHARACTERISTICS 62
- 13.ORDERING INFORMATION 63
- 14.REFERENCES 63
- 15.REVISION HISTORY 64
- DS700PP1 65 65
- 66 DS700PP1 66
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