Cirrus-logic CS53L21 User Manual Page 30
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30 DS700PP1
CS53L21
4.5.1 Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the A/D is automatically determined based on
the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then
require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-alone
control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
4.5.2 Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the A/D operates in single-speed only. In Software Mode, the A/D operates in either
quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
Auto-Detect QSM HSM SSM DSM
Disabled
(Software
Mode only)
512, 768, 1024, 1536,
2048, 3072
256, 384, 512, 768,
1024, 1536
128, 192, 256, 384,
512, 768
128, 192, 256, 384
Enabled
1024, 1536, 2048*,
3072*
512, 768, 1024*, 1536* 256, 384, 512*, 768* 128, 192, 256*, 384*
*MCLKDIV2 must be enabled.
Table 3. MCLK/LRCK Ratios
÷ 256
÷ 128
÷ 512
LRCK Output
(Equal to Fs)
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
SCLK Output
÷ 2
÷ 1
0
1
MCLK
MCLKDIV2
÷ 128
00
÷ 4
÷ 2
÷ 8
Single
Speed
Quarter
Speed
Half
Speed
01
10
11
÷ 2
00
Double
Speed
Double
Speed
SPEED[1:0]
Figure 13. Master Mode Timing
- FEATURES 1
- SYSTEM FEATURES 1
- ™ Control) 1
- APPLICATIONS 2
- GENERAL DESCRIPTION 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 6 DS700PP1 6
- 6
- Pin Name # Pin Description 6
- DS700PP1 7 7
- DS700PP1 9 9
- 10 DS700PP1 10
- ABSOLUTE MAXIMUM RATINGS 11
- SDOUT Code with HPF On 12
- Repeated 16
- = 100 μA) 18
- (Note 14) 18
- = -100 μA) 18
- POWER CONSUMPTION 19
- 4. APPLICATIONS 20
- 4.2 Hardware Mode 21
- Software 22
- Controls: 22
- 4.3.3 Digital Routing 23
- 4.3.4 Differential Inputs 23
- 24 DS700PP1 24
- 4.3.6 MIC & PGA Gain 25
- ADCx_ATT[7:0] and 26
- PGAx_VOL[4:0] volume 26
- ALCx is enabled 26
- 4.3.8 Noise Gate 27
- 4.4 Signal Processing Engine 28
- 4.4.1 Volume Controls 28
- 4.4.2 Mono Channel Mixer 28
- 4.5 Serial Port Clocking 29
- 4.5.1 Slave 30
- 4.5.2 Master 30
- 4.6 Digital Interface Formats 31
- 4.7 Initialization 32
- 4.10 Software Mode 34
- 4.10.1 SPI Control 34
- 4.10.2 I²C Control 34
- 4 5 6 7 24 25 35
- 4.10.3.1 Map Increment (INCR) 36
- 5. REGISTER QUICK REFERENCE 37
- 38 DS700PP1 38
- DS700PP1 39 39
- 6. REGISTER DESCRIPTION 40
- 76543210 41
- Reserved M/S 43
- 6.5 MIC Control (Address 05h) 44
- 6.6 ADC Control (Address 06h) 45
- AINx_MUX[1:0] 47
- PDN_PGAx 47
- 6.8 SPE Control (Address 09h) 48
- 7. ANALOG PERFORMANCE PLOTS 56
- 8.1 Auto Detect Enabled 57
- 8.2 Auto Detect Disabled 58
- 9. PCB LAYOUT CONSIDERATIONS 59
- 10.DIGITAL FILTERS 60
- 11.PARAMETER DEFINITIONS 61
- 12.PACKAGE DIMENSIONS 62
- THERMAL CHARACTERISTICS 62
- 13.ORDERING INFORMATION 63
- 14.REFERENCES 63
- 15.REVISION HISTORY 64
- DS700PP1 65 65
- 66 DS700PP1 66
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