Cirrus-logic CS53L21 User Manual Page 18
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18 DS700PP1
CS53L21
DC ELECTRICAL CHARACTERISTICS
(AGND = 0 V; all voltages with respect to ground.)
14. The DC current draw represents the allowed current draw from the VQ pin due to typical leakage
through electrolytic de-coupling capacitors.
15. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the capacitance will also
increase the PSRR.
DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS
16. See “Digital I/O Pin Characteristics” on page 8 for serial and control port power rails.
Parameters Min Typ Max Units
VQ Characteristics
Nominal Voltage
Output Impedance
DC Current Source/Sink (Note 14)
-
-
-
0.5•VA
23
-
-
-
10
V
kΩ
μA
FILT+
-VA-V
MIC BIAS Characteristics
Nominal Voltage MICBIAS_LVL[1:0] = 00
MICBIAS_LVL[1:0] = 01
MICBIAS_LVL[1:0] = 10
MICBIAS_LVL[1:0] = 11
DC Current Source
Power Supply Rejection Ratio (PSRR) 1 kHz
-
-
-
-
-
-
0.8•VA
0.7•VA
0.6•VA
0.5•VA
-
50
-
-
-
-
1
-
V
V
V
V
mA
dB
Power Consumption (Normal Operation Worse Case) 1 kHz
--30mW
Power Supply Rejection Ratio (PSRR) (Note 15) 1 kHz
-60-dB
Parameters (Note 16) Symbol Min Max Units
Input Leakage Current
I
in
-±10μA
Input Capacitance
-10pF
1.8 V - 3.3 V Logic
High-Level Output Voltage (I
OH
= -100 μA)
V
OH
VL - 0.2 - V
Low-Level Output Voltage
(I
OL
= 100 μA)
V
OL
-0.2V
High-Level Input Voltage
V
IH
0.68•VL - V
Low-Level Input Voltage
V
IL
- 0.32•VL V
- FEATURES 1
- SYSTEM FEATURES 1
- ™ Control) 1
- APPLICATIONS 2
- GENERAL DESCRIPTION 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 6 DS700PP1 6
- 6
- Pin Name # Pin Description 6
- DS700PP1 7 7
- DS700PP1 9 9
- 10 DS700PP1 10
- ABSOLUTE MAXIMUM RATINGS 11
- SDOUT Code with HPF On 12
- Repeated 16
- = 100 μA) 18
- (Note 14) 18
- = -100 μA) 18
- POWER CONSUMPTION 19
- 4. APPLICATIONS 20
- 4.2 Hardware Mode 21
- Software 22
- Controls: 22
- 4.3.3 Digital Routing 23
- 4.3.4 Differential Inputs 23
- 24 DS700PP1 24
- 4.3.6 MIC & PGA Gain 25
- ADCx_ATT[7:0] and 26
- PGAx_VOL[4:0] volume 26
- ALCx is enabled 26
- 4.3.8 Noise Gate 27
- 4.4 Signal Processing Engine 28
- 4.4.1 Volume Controls 28
- 4.4.2 Mono Channel Mixer 28
- 4.5 Serial Port Clocking 29
- 4.5.1 Slave 30
- 4.5.2 Master 30
- 4.6 Digital Interface Formats 31
- 4.7 Initialization 32
- 4.10 Software Mode 34
- 4.10.1 SPI Control 34
- 4.10.2 I²C Control 34
- 4 5 6 7 24 25 35
- 4.10.3.1 Map Increment (INCR) 36
- 5. REGISTER QUICK REFERENCE 37
- 38 DS700PP1 38
- DS700PP1 39 39
- 6. REGISTER DESCRIPTION 40
- 76543210 41
- Reserved M/S 43
- 6.5 MIC Control (Address 05h) 44
- 6.6 ADC Control (Address 06h) 45
- AINx_MUX[1:0] 47
- PDN_PGAx 47
- 6.8 SPE Control (Address 09h) 48
- 7. ANALOG PERFORMANCE PLOTS 56
- 8.1 Auto Detect Enabled 57
- 8.2 Auto Detect Disabled 58
- 9. PCB LAYOUT CONSIDERATIONS 59
- 10.DIGITAL FILTERS 60
- 11.PARAMETER DEFINITIONS 61
- 12.PACKAGE DIMENSIONS 62
- THERMAL CHARACTERISTICS 62
- 13.ORDERING INFORMATION 63
- 14.REFERENCES 63
- 15.REVISION HISTORY 64
- DS700PP1 65 65
- 66 DS700PP1 66
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