Cirrus-logic CS42L73 User Manual download pdf (Page 90)

90 DS882F1

CS42L73

6.12.2 ASP Sample Rate

Identifies the ASP audio sample rate.

6.12.3 ASP SCLK Source Equals MCLK

Applicable only if A_M/S = 1b (Master Mode). Configures the ASP_SCLK signal source and speed.

6.13 ASP Master Mode Clocking Control (Address 0Fh)

Also refer to ASP Master Mode Clocking relevant control bits “ASP SCLK Source Equals MCLK” on

page 90.

6.13.1 ASP Master/Slave Mode

Configures the ASP clock source (direction).

6.13.2 ASP Master Mode Clock Control Dividers

Provides the appropriate divide ratios for all supported serial port master mode clock timings.

ASPFS[3:0] Audio Sample Rate for ASP

0000 Don’t know

0001 8.00 kHz

0010 11.025 kHz

0011 12.000 kHz

0100 16.000 kHz

0101 22.050 kHz

0110 24.000 kHz

0111 32.000 kHz

1000 44.100 kHz

1001 48.000 kHz

1010 to 1111 Reserved

Application: Refer to section “Asynchronous Sample Rate Converters (ASRCs)” on page 59.

A_SCK=MCK[1:0] Output ASP_SCLK Sourcing Mode

SCLK  MCLK (SCLK = ~64•Fs) Mode

01 Reserved

10 SCLK = MCLK Mode

11 SCLK = Pre-MCLK Mode

Application: Refer to section “SCLK = MCLK Modes” on page 53.

76543210

A_M/S Reserved A_MMCC5 A_MMCC4 A_MMCC3 A_MMCC2 A_MMCC1 A_MMCC0

A_M/S

Serial Port Clocks

0 Slave (Input)

1 Master (Output)

Application: Refer to section “Master and Slave Timing” on page 52.

A_MMCC[5:0] Master Mode Clock Control Settings

01 0101 Refer to section “Serial Port Sample Rates and Master Mode Settings” on page 53

Others

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Cirrus-logic CS42L73 User Manual Page 90