Cirrus-logic CS42L73 User Manual download pdf (Page 58)

58 DS882F1

CS42L73

The CS42L73 will always transmit 24-bit-deep data if at least 24 serial clocks are present per channel

sample. If less than 24 serial clocks are present per channel sample, it will output as many bits as there

are clocks. If there are more than 24 serial clocks per channel sample, it will output zeros for the additional

clock cycles after the 24th bit. The receiving device is expected to load the data in MSB-to-LSB order until

its word depth is reached, whereupon it must discard any remaining LSBs from the interface.

The CS42L73 will always attempt to receive 24 bits of data, regardless of the sourcing device’s da-

ta-bit-depth. If there are less than 24 serial clock cycles per channel sample, it will load the MSBs of its

internal 24-bit-wide word with the data associated with all the serial clocks and then augment this data by

filling in the LSBs with zeros. If there are more than 24 serial clock cycles per channel sample, all the re-

ceived data after the 24th bit is discarded.

For instance, if the source data is 16 bits long and the serial clock toggles for 20 cycles per channel, the

16 MSBs of the 24-bit internal data word will be loaded with the 16 bits of source data, whatever follows

on the xSP_SDIN input for the remaining 4 cycles will be loaded into the next 4 bits, and then the 4 LSBs

will be filled with zeros.

4.8.8.2 PCM Format Bit Depths

For the PCM interface format (refer to section “PCM Format” on page 55), the data bit depth is always 16

bits per sample. Given this unambiguous word length, the following simpler process is used to handle the

fact that less than 24 bits are used.

The CS42L73 places the 16 MSBs of its internal 24-bit-wide word into the shorter transmitted (xSP_SD-

OUT) word and, if, before the next sample word sync pulse, there are additional serial clocks after the

16th transmitted bit, the data associated with the additional serial clocks is to be discarded by the receiv-

ing device.

The CS42L73 loads the 16-bit received (xSP_SDIN) word into the MSBs of its internal 24-bit-wide word

and then augments the received data with zeros to fill the 8 LSBs of the internal 24-bit word.

Referenced Control Register Location

MCLKSEL ...........................

PDN_VSP ...........................

PDN_ASP_SDOUT.............

PDN_ASP_SDIN.................

PDN_XSP_SDOUT.............

PDN_XSP_SDIN.................

3ST_XSP ............................

XSPDIF ...............................

X_PCM_MODE[1:0]............

XPCM_BIT_ORDER ...........

X_SCK=MCK[1:0] ...............

X_M/S

.................................

X_MMCC[5:0] .....................

3ST_ASP ............................

A_SCK=MCK[1:0] ...............

A_M/S

.................................

A_MMCC[5:0] .....................

3ST_VSP ............................

VSPDIF ...............................

V_PCM_MODE[1:0]............

VPCM_BIT_ORDER ...........

V_SDIN_LOC......................

V_SCK=MCK[1:0] ...............

V_M/S

.................................

V_MMCC[5:0] .....................

“Master Clock Source Selection” on page 87

“Power Down VSP” on page 83

“Power Down ASP SDOUT Path” on page 83

“Power Down ASP SDIN Path” on page 83

“Power Down XSP SDOUT Path” on page 83

“Power Down XSP SDIN Path” on page 83

“Tristate XSP Interface” on page 88

“XSP Digital Interface Format” on page 88

“XSP PCM Interface Mode” on page 88

“XSP PCM Format Bit Order” on page 88

“XSP SCLK Source Equals MCLK” on page 88

“XSP Master/Slave Mode” on page 89

“XSP Master Mode Clock Control Dividers” on page 89

“Tristate ASP Interface” on page 89

“ASP SCLK Source Equals MCLK” on page 90

“ASP Master/Slave Mode” on page 90

“ASP Master Mode Clock Control Dividers” on page 90

“Tristate VSP Interface” on page 91

“VSP Digital Interface Format” on page 91

“VSP PCM Interface Mode” on page 91

“VSP PCM Format Bit Order” on page 91

“VSP SDIN Location” on page 92

“VSP SCLK Source Equals MCLK” on page 92

“VSP Master/Slave Mode” on page 92

“VSP Master Mode Clock Control Dividers” on page 92

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 138 139

Comments to this Manuals

No comments

Cirrus-logic CS42L73 User Manual Page 58

Comments to this Manuals

Related products and manuals for Hardware Cirrus-logic CS42L73