Cirrus-logic CS42L73 User Manual download pdf (Page 37)

DS882F1 37

CS42L73

SWITCHING SPECIFICATIONS—DIGITAL MIC INTERFACE

Test conditions: Inputs: Logic 0 = GND = DGND = 0 V, Logic 1 = VL; T

= +25 C; C

LOAD

= 30 pF.

Notes:

54. The output clock frequency will follow the master clock (MCLK) rate divided down as per the tables in sections “Digital

Microphone (DMIC) Interface” on page 60. Any deviation of the Master Clock source from the nominal supported rates

will be directly imparted to the output clock rate by the same factor (e.g., +100 ppm offset in the frequency of MCLK1/

MCLK2 will become a +100 ppm offset in DMIC_CLK).

55. Data is valid at the high-level input voltage (V

) and the low-level input voltage (V

), which are specified in “Digital In-

terface Specifications and Characteristics” on page 35.

Parameters (Note 2) Symbol Min Max Units

Output Clock (DMIC_CLK) Frequency

1/t

(Note 54)

kHz

DMIC_CLK Duty Cycle

DMIC_CLK Rise Time (10% to 90% of VL)

-22

DMIC_CLK Fall Time (90% to 10% of VL)

-10

DMIC_SD Setup Time Before DMIC_CLK Rising Edge (Note 55)

s(SD-CLKR)

10 -

DMIC_SD Hold Time After DMIC_CLK Rising Edge (Note 55)

h(CLKR-SD)

DMIC_SD Setup Time Before DMIC_CLK Falling Edge (Note 55)

s(SD-CLKF)

10 -

DMIC_SD Hold Time After DMIC_CLK Falling Edge (Note 55)

h(CLKF-SD)

600 -

DMIC_SCLK

DMIC_SD

h(CLKR-SD)

h(CLKF-SD)

s(SD-CLKR)

s(SD-CLKF)

90%

10%

Figure 11. Digital Mic Interface Timing

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 138 139

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Cirrus-logic CS42L73 User Manual Page 37

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