Cirrus-logic CS42L73 User Manual Page 38
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38 DS882F1
CS42L73
SWITCHING SPECIFICATIONS—SERIAL PORTS—I²S FORMAT
Test conditions: Inputs: Logic 0 = GND = DGND = 0 V, Logic 1 = VL; T
A
= +25 C; x = X, A, or V; xSP_LRCK, xSP_SCLK, xSP_
SDOUT; C
LOAD
= 15 pF.
Notes:
56. In Master Mode, the output sample rate follows the Master Clock source (MCLK1 or MCLK2) rate divided down per “In-
ternal Master Clock Generation” on page 42 and “Serial Port Sample Rates and Master Mode Settings” on page 53.
Any Master Clock source deviation from the nominal supported rates is directly imparted to the output sample rate by
the same factor (e.g., +100 ppm offset in the MCLK1/MCLK2 frequency becomes a +100 ppm xSP_LRCK offset).
57. Maximum frequency for highest supported nominal rate is indicated. The supported nominal rates are described in sec-
tion “SCLK = MCLK Modes” on page 53.
Parameters (Note 2) Symbol Min Max Units
Slave Mode
Input sample Rate (xSP_LRCK) (Note 24) (Note 53)
Fs
ext-s
-
50
kHz
xSP_LRCK Duty Cycle
-4555
%
xSP_SCLK Frequency (Note 10)
1/t
Ps
- 68•Fs
Hz
xSP_SCLK Duty Cycle
-4555
%
xSP_LRCK Setup Time Before xSP_SCLK Rising Edge
t
ss(LK-SK)
40 -
ns
xSP_LRCK Hold Time After xSP_SCLK Rising Edge
t
hs(SK-LK)
20 -
ns
xSP_SDOUT Setup Time Before xSP_SCLK Rising Edge
t
ss(SDO-SK)
20 -
ns
xSP_SDOUT Hold Time After xSP_SCLK Rising Edge
t
hs(SK-SDO)
30 -
ns
xSP_SDIN Setup Time Before xSP_SCLK Rising Edge
t
ss(SDI-SK)
20 -
ns
xSP_SDIN Hold Time After xSP_SCLK Rising Edge
t
hs(SK-SDI)
20 -
ns
Master Mode
Output Sample Rate (xSP_LRCK) (Note 24)
Fs
ext-m
-
(Note 56)
kHz
xSP_LRCK Duty Cycle
-
45
55
%
xSP_SCLK Frequency “SCLK MCLK” Mode
“SCLK = MCLK” Mode
“SCLK = Pre-MCLK” Mode (Note 57)
1/t
Pm
-
-
-
68•Fs
ext-m
MCLK
12.1
Hz
Hz
MHz
xSP_SCLK Duty Cycle
-4555
%
xSP_LRCK Setup Time Before xSP_SCLK Rising Edge
t
sm(LK-SK)
35 -
ns
xSP_LRCK Hold Time After xSP_SCLK Rising Edge
t
hm(SK-LK)
20 -
ns
xSP_SDOUT Setup Time Before xSP_SCLK Rising Edge
t
sm(SDO-SK)
20 -
ns
xSP_SDOUT Hold Time After xSP_SCLK Rising Edge
t
hm(SK-SDO)
30 -
ns
xSP_SDIN Setup Time Before xSP_SCLK Rising Edge
t
sm(SDI-SK)
20 -
ns
xSP_SDIN Hold Time After xSP_SCLK Rising Edge
t
hm(SK-SDI)
20 -
ns
t
h(SK-SDO)
//
t
s(SDI-SK)
xSP_LRCK
xSP_SCLK
xSP_SDOUT
xSP_SDIN
t
P
t
h(SK-SDI)
t
s(SDO-SK)
Note:
x = X, A, or V;
= “s” or “m”
t
s(LK-SK)
t
h(SK-LK)
Figure 12. Serial Port Interface Timing—I²S Format
- Product Overview 1
- Ultralow Power Consumption 1
- Applications 1
- System Features 1
- General Description 3
- TABLE OF CONTENTS 4
- LIST OF FIGURES 9
- LIST OF TABLES 10
- 12 DS882F1 12
- DS882F1 13 13
- 1.3 Pin/Ball Descriptions 14
- DS882F1 15 15
- 2. TYPICAL CONNECTION DIAGRAM 17
- ABSOLUTE MAXIMUM RATINGS 20
- DC ELECTRICAL CHARACTERISTICS 21
- 22 DS882F1 22
- CHARACTERISTICS 24
- MIC BIAS CHARACTERISTICS 26
- --70-60dB 27
- 0.73•VA 0.79•VA 0.85•VA V 27
- Test Load 28
- Measurement 28
- FILTER CHARACTERISTICS 33
- POWER CONSUMPTION 34
- DMIC_SCLK 37
- = “s” or “m” 38
- Repeated 40
- 4. APPLICATIONS 41
- 4.5 Class H Amplifier 44
- 4.5.1 Power Control Options 44
- 48 DS882F1 48
- 4.5.3 Efficiency 49
- 4.6 DAC Limiter 49
- LIMRRATEx[2:0] 50
- LIMARATEx[2:0] 50
- 4.8 Serial Ports 51
- 4.8.1 Power Management 51
- 4.8.2 I/O 51
- 4.8.3 High-impedance Mode 52
- 4.8.4 Master and Slave Timing 52
- 4.8.4.1 SCLK = MCLK Modes 53
- 4.8.6 Formats 54
- 4.8.6.1 I²S Format 55
- 4.8.6.2 PCM Format 55
- 4.8.7 Mono/Stereo 57
- 4.8.8 Data Bit Depths 57
- 4.8.8.1 I²S Format Bit Depths 57
- 4.8.8.2 PCM Format Bit Depths 58
- 4.10 Input Paths 59
- DMIC_CLK 60
- 4.11 Digital Mixer 61
- 62 DS882F1 62
- 4.11.1 Mono and Stereo Paths 63
- 4.15 Interrupts 70
- 4.16 Control Port Operation 71
- 4.16.1 I²C Control 71
- 7 6 5 4 3 2 1 0 72
- 4.17 Fast Start Mode 73
- SPKLINEOUT 74
- EARSPKOUT 74
- Normal audioNo audio 75
- Clipped/Ramping audio 75
- 5. REGISTER QUICK REFERENCE 76
- DS882F1 77 77
- 78 DS882F1 78
- DS882F1 79 79
- 80 DS882F1 80
- (Read Only) 80
- 6. REGISTER DESCRIPTION 81
- 6.12.2 ASP Sample Rate 90
- 6.13.1 ASP Master/Slave Mode 90
- 6.14.5 VSP SDIN Location 92
- 6.15.1 VSP Master/Slave Mode 92
- 6.16.1 VSP Sample Rate 93
- 6.16.2 XSP Sample Rate 93
- 6.17.1 Digital Swap/Mono 94
- 6.17.2 Input Path Channel B=A 94
- 6.17.4 PGA Soft-Ramp 95
- 6.17.5 Analog Zero Cross 95
- 6.17.6 Digital Soft-Ramp 96
- 6.19.1 Mic PREAMP x Volume 98
- 6.19.2 PGAx Volume 98
- DS882F1 99 99
- DS882F1 103 103
- 104 DS882F1 104
- 76543210 110
- (Address 2Eh) 112
- 6.44.3 ALCx Soft-Ramp Disable 116
- 6.45.3 Mixer Soft-Ramp Enable 117
- 118 DS882F1 118
- DS882F1 119 119
- 120 DS882F1 120
- DS882F1 121 121
- 7. PCB LAYOUT CONSIDERATIONS 125
- 8. PERFORMANCE DATA 126
- DS882F1 127 127
- 128 DS882F1 128
- 8.3 Core Circuitry Attributes 129
- 8.3.1 ASRC Attributes 129
- 8.3.1.1 Response 129
- 8.3.1.2 Group Delay 130
- 8.3.1.3 Lock Time 130
- DS882F1 131 131
- 8.4.2 DAC HPF Response 132
- 8.4.4 Startup Times 133
- 9. PARAMETER DEFINITIONS 134
- 10.PACKAGE DIMENSIONS 135
- BUMP SIDESIDE VIEW 136
- TOP SIDE 136
- 11.THERMAL CHARACTERISTICS 137
- 12.ORDERING INFORMATION 137
- 13.REFERENCES 137
- 14.REVISION HISTORY 138
- DS882F1 139 139
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