Cirrus-logic CS4207 User Manual download pdf (Page 32)

32 DS880F4

CS4207

If the codec has detected that the link is entering a Link Reset state (see description below), all Unsolicited

Response requests will be buffered. Once the link is in the Link Reset state, with RESET# asserted low,

the codec will request a power state change and initialization request. Following the codec initialization

cycle where a unique address is provided to the CS4207, the codec will then wait for the first verb to be

received before issuing the Unsolicited Response to prevent the response from being lost due to software

transition to active power state.

The Link Reset entry sequence is defined as follows:

1. The HD Audio Bus controller synchronously completes the current frame but does not signal Frame

Sync (SYNC) during the last eight SDO bit times.

2. The HD Audio Bus controller synchronously asserts RESET# four (or more) BITCLK cycles after the

completion of the current frame.

3. BITCLK is stopped a minimum of four clocks, four rising edges, after the assertion of RESET#.

In the event of a system bus (PCI Bus) reset, the above sequence does not complete, and RESET# is

asynchronously asserted immediately and unconditionally.

When the codec returns to D0 from the D3 lower power state, the state of the presence detection bits will

be correct. If the codec power has been removed, the state of the presence detection bits will be reset to

the default value and the codec

WILL NOT report this by setting the PS-SettingsReset bit for the affected

Pin Widget(s). (HDA015-B, March 1, 2007 says that the PS-SettingsReset bit will be set for the affected

Pin widget).

5.1.2 S/PDIF Receiver Presence Detect

The presence detect scheme for the S/PDIF Receiver will use the logic state transition of the “LOCK” or

“UNLOCK” indicator for the incoming digital stream. The “LOCK” and “UNLOCK” indicators are sticky bits

(edge-triggered) which indicate the current state of the receiver. These bits are located in the Vendor Pro-

cessing Widget, see “S/PDIF RX/TX Interface Status (CIR = 0000h)” on p 129. When the S/PDIF Receiver

Input Converter Widget is “enabled” and the “LOCK” indicator is a “1”, then the Presence Detect bit in the

Pin Sense register will be set to ‘1’. The S/PDIF IN Converter Widget (NID=07h) and the S/PDIF Receiver

pin widget (NID=0Fh) must be in the D0 state to support presence detect using this method described.

With an incoming valid S/PDIF signal applied to the SPDIF_IN pin, the “LOCK” status will be valid approx-

imately 200 S/PDIF frames following the receiver being enabled.

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Cirrus-logic CS4207 User Manual Page 32