Cirrus-logic CRD5376 User Manual

Copyright © Cirrus Logic, Inc. 2007(All Rights Reserved)www.cirrus.comCRD5376Multichannel Seismic Reference DesignFeaturesz Four Channel Seismic Acqui

CRD537610 DS612RD2• Once the Setup panel is set, select Configure on the Digital Filter sub-panel.• After digital filter configuration is complete, cl

CRD5376DS612RD2 112. HARDWARE DESCRIPTION2.1 Block Diagram Major blocks of the CRD5376 reference design include:• CS3301A Geophone Amplifier (2x)• CS3

CRD537612 DS612RD22.2 Analog Hardware2.2.1 Analog Inputs2.2.1.1 External Inputs - INAExternal signals into CRD5376 are from two major classes of senso

CRD5376DS612RD2 13Discrete switching diodes quickly clamp the analog inputs to the power supply rails when the input voltagespikes. These diodes are r

CRD537614 DS612RD22.2.1.6 Common Mode BiasDifferential analog signals into the CS3301A/02A amplifiers need to be biased to the center of the powersupp

CRD5376DS612RD2 15Using this level-shifting 3-to-8 demultiplexer scheme allows flexible control of the analog switches withoutdirectly coupling them t

CRD537616 DS612RD22.2.2 Differential AmplifiersThe CS3301A/02A amplifiers act as a low-noise gain stage for internal or external differential analog s

CRD5376DS612RD2 172.2.2.2 Rough-Fine Outputs - OUTR, OUTFThe analog outputs of the CS3301A/02A differential amplifiers are split into rough charge and

CRD537618 DS612RD22.2.4 Delta-Sigma Test DACThe CS4373A test DAC creates differential analog signals for system tests. Multiple test modes are avail-

CRD5376DS612RD2 192.2.5.1 VREF_MOD12, VREF_MOD34, VREF_DACThe voltage reference output is provided to the CS5372A ∆Σ modulators and the CS4373A test D

CRD53762 DS612RD2REVISION HISTORYRevision Date ChangesRD1 FEB 2006 Initial Release.RD2 NOV 2007 BOM change to latest revision of silicon. Minor layout

CRD537620 DS612RD2Data is collected through the SD port.Modulator ∆Σ data is input through the modulator interface.Test DAC ∆Σ data is generated by th

CRD5376DS612RD2 21The secondary serial port (SPI 2) and boundary scan JTAG port are unused on CRD5376.2.3.1.1 MCLK vs. MCLK/2 UsageThe CS5376A digital

CRD537622 DS612RD2CRD5376, as an input from the microcontroller to initiate data transactions on command or from theMCLK/2 clock to initiate data tran

CRD5376DS612RD2 23C8051F320 has dedicated pins for power and the USB connection, plus 25 general purpose I/O pins thatconnect to the various internal

CRD537624 DS612RD2Many connections to the C8051F320 microcontroller are inactive by default, but are provided for conve-nience during custom reprogram

CRD5376DS612RD2 252.3.2.5 Timebreak SignalBy default, the C8051F320 microcontroller sends the TIMEB signal to the digital filter for the first collect

CRD537626 DS612RD2The PLL on CRD5376 uses a voltage controlled crystal oscillator (VCXO) to minimize jitter, and has a sin-gle gate phase/frequency de

CRD5376DS612RD2 272.3.4.1 CLK, SYNCClock and synchronization telemetry signals into CRD5376 are received through RS-485 twisted pairs.These signals ar

CRD537628 DS612RD2version data. Address assignment can be either dynamic or static, depending how the telemetry systemis to be implemented.Dynamic add

CRD5376DS612RD2 292.4.1 Analog Voltage RegulatorsLinear voltage regulators create the positive and negative analog power supply voltages to the analog

CRD5376DS612RD2 3TABLE OF CONTENTS1. INITIAL SETUP ...

CRD537630 DS612RD2CRD5376 layer 5 is a solid ground plane without splits or routing. A solid ground plane provides the bestreturn path for bypassed n

CRD5376DS612RD2 312.5.3 Bypass CapacitorsEach device power supply pin includes 0.1 µF bypass capacitors placed as close as possible to the pin.Each po

CRD537632 DS612RD23. SOFTWARE DESCRIPTION3.1 Menu BarThe menu bar is always present at the top of the software panels and provides typical File and He

CRD5376DS612RD2 333.2 About PanelThe About panel displays copyright information for the Cirrus Seismic Evaluation software.Click OK to exit this panel

CRD537634 DS612RD23.3 Setup PanelThe Setup panel initializes the evaluation system to perform data acquisition. It consists of the followingsub-panels

CRD5376DS612RD2 353.3.1 USB PortThe USB Port sub-panel sets up the USB communication interface between the PC and the target board.Control Description

CRD537636 DS612RD23.3.2 Digital FilterThe Digital Filter sub-panel sets up the digital filter configuration options.By default the Digital Filter sub-

CRD5376DS612RD2 373.3.3 Analog Front EndThe Analog Front End sub-panel configures the amplifier, modulator, and test DAC pin options. Pin op-tions are

CRD537638 DS612RD23.3.5 Gain/OffsetThe Gain / Offset sub-panel controls the digital filter GAIN and OFFSET registers for each channel.The OFFSET and G

CRD5376DS612RD2 393.3.6 Data CaptureThe Data Capture sub-panel collects samples from the target board and sets analysis parameters.When the Capture bu

CRD53764 DS612RD23.4.7 Harmonics ... 443.4.8

CRD537640 DS612RD23.3.7 External MacrosMacros are generated within the Macros sub-panel on the Control panel. Once a macro has been builtit can either

CRD5376DS612RD2 413.4 Analysis PanelThe Analysis panel is used to display the analysis results on collected data. It consists of the followingcontrols

CRD537642 DS612RD23.4.1 Test SelectThe Test Select control sets the type of analysis to be run on the collected data set.Control DescriptionTime Domai

CRD5376DS612RD2 433.4.2 StatisticsThe Statistics control displays calculated statistics for the selected analysis channel. For multichanneldata captur

CRD537644 DS612RD23.4.4 CursorThe Cursor control is used to identify a point on the graph using the mouse and then display its plot values.When any po

CRD5376DS612RD2 453.5 Control PanelThe Control panel is used to write and read register settings and to send commands to the digital filter.It consist

CRD537646 DS612RD23.5.1 DF RegistersThe DF Registers sub-panel writes and reads registers within the digital filter. Digital filter registers con-trol

CRD5376DS612RD2 473.5.4 MacrosThe Macros sub-panel is designed to write a large number of registers with a single command. This al-lows the target eva

CRD537648 DS612RD23.5.6 CustomizeThe Customize sub-panel sends commands to upload custom FIR and IIR filter coefficients, upload cus-tom test bit stre

CRD5376DS612RD2 494. BILL OF MATERIALS CIRRUS LOGICCRD5376_REV_D1.PLBILL OF MATERIAL (Page 1 of 2)Cirrus P/N Rev Description Qty Reference Designator

CRD5376DS612RD2 51. INITIAL SETUP1.1 Kit ContentsThe CRD5376 reference design kit includes:• CRD5376 reference design board• USB cable (A to mini-B)•

CRD537650 DS612RD2CIRRUS LOGICCRD5376_REV_D1.PLBILL OF MATERIAL (Page 2 of 2)Cirrus P/N Rev Description Qty Reference Designator MFG MFG P/N Notes061-

CRD5376DS612RD2 515. LAYER PLOTS

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CRD5376DS612RD2 576. SCHEMATICS

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CRD53766 DS612RD21.2.1 Default Jumper Settings* indicates the default jumper installation for CRD5376. Amplifier CS3301A CS3302ACH1 U16 *R128 + *R84

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CRD5376DS612RD2 71.3 Software Setup1.3.1 PC RequirementsThe PC hardware requirements for the Cirrus Seismic Evaluation system are:• Windows XP®, Windo

CRD53768 DS612RD2CRD5376 as an unknown USB device.• If prompted for a USB driver, skip to the next step. If not, using Windows Hardware Device Manager

CRD5376DS612RD2 91.4 Self-Testing CRD5376Noise and distortion self-tests can be performed once hardware and software setup is complete.First, initiali