Cirrus-logic CRD5376 User Manual Page 28
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CRD5376
28 DS612RD2
version data. Address assignment can be either dynamic or static, depending how the telemetry system
is to be implemented.
Dynamic address assignment uses daisy-chained I2C connections to assign an address to each mea-
surement node. Once a node receives an address, it enables the I2C bypass switches to the next node
so it can be assigned an address.
Static address assignment has a serial number assigned to each node during manufacturing. When
placed in the network the location is recorded and a master list of serial numbers vs. location is main-
tained. Alternately, a location dependent serial number can be assigned during installation.
2.3.5 UART Connection
A UART connection on CRD5376 provides a low-speed standardized connection for telemetry solutions
not using I2C. UART connections are provided for custom programming convenience only and are not
directly supported by the CRD5376 PC evaluation software or microcontroller firmware.
2.3.6 External Connector
Power supplies and telemetry signals route to a 20-pin double row connector with 0.1" spacing (J8). This
header provides a compact standardized connection to the CRD5376 external signals.
2.4 Power Supplies
Power is supplied to CRD5376 through the +3.3 V and -3.3 V voltage inputs on the external connector
(J8), which are typically from an external AC-DC or DC-DC converter. Digital circuitry on CRD5376 is driv-
en directly from the +3.3 V input, while linear regulators create +2.5 V and - 2.5 V analog power supplies
from +3.3 V and -3.3 V.
The +3.3 V and -3.3 V power supply inputs have zener protection diodes that limit the maximum input volt-
ages to +5 V or -5 V with respect to ground. Each input also has 100 uF bulk capacitance for bypassing
and to help settle transients and another 0.01 uF capacitor to bypass high frequency noise.
Specification Value
UART Connections, 2 wires each TX/GND, RX/GND
Pins Name Signal
1, 2 CLK+, CLK- Clock Input
3, 4 SYNC+, SYNC- Synchronization Input
5, 6 SCL+, SCL- I2C Clock
7, 8 SDA+, SDA- I2C Data
9, 10 BYP_SDA+, BYP_SDA- I2C Data Bypass
11, 12 BYP_SCL+, BYP_SCL- I2C Clock Bypass
13, 14 TX, GND UART transmit
15, 16 RX, GND UART receive
17, 18 -3.3V, GND Negative Power Supply
19, 20 +3.3V, GND Positive Power Supply
- Features 1
- General Description 1
- REVISION HISTORY 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 4
- LIST OF TABLES 4
- 1. INITIAL SETUP 5
- 1.1 Kit Contents 5
- 1.2 Hardware Setup 5
- 1.2.1 Default Jumper Settings 6
- 1.3 Software Setup 7
- 1.3.1 PC Requirements 7
- 8 DS612RD2 8
- 1.4 Self-Testing CRD5376 9
- 1.4.1 Noise Test 9
- 1.4.2 Distortion Test 10
- 2. HARDWARE DESCRIPTION 11
- 2.1 Block Diagram 11
- 2.2.1.1 External Inputs - INA 12
- 2.2.1.4 Input Protection 12
- 2.2.1.5 Input RC Filters 13
- 2.2.1.7 Analog Test Switches 14
- 2.2.1.6 Common Mode Bias 14
- 2.2.2.3 Anti-alias RC Filters 17
- 2.2.3.2 Offset Enable - OFST 17
- 2.2.4 Delta-Sigma Test DAC 18
- 2.2.5 Voltage Reference 18
- 2.3 Digital Hardware 19
- 2.3.1 Digital Filter 19
- 20 DS612RD2 20
- 2.3.1.1 MCLK vs. MCLK/2 Usage 21
- 22 DS612RD2 22
- CS5376A uController MCLK/2 22
- SDTKI R74 R83 22
- DS612RD2 23 23
- 2.3.2.1 SPI Interface 24
- 2.3.2.2 USB Interface 24
- 2.3.2.3 Reset Source 24
- 2.3.2.4 Clock Source 24
- 2.3.2.5 Timebreak Signal 25
- 2.3.2.6 C2 Debug Interface 25
- 2.3.4 RS-485 Telemetry 26
- 2.3.4.1 CLK, SYNC 27
- 2.3.5 UART Connection 28
- 2.3.6 External Connector 28
- 2.4 Power Supplies 28
- DS612RD2 29 29
- 2.5.2 Differential Pairs 30
- 2.5.3 Bypass Capacitors 31
- 3. SOFTWARE DESCRIPTION 32
- 3.1 Menu Bar 32
- 3.2 About Panel 33
- 3.3 Setup Panel 34
- 3.3.1 USB Port 35
- 3.3.2 Digital Filter 36
- 3.3.3 Analog Front End 37
- 3.3.4 Test Bit Stream 37
- 3.3.5 Gain/Offset 38
- 3.3.6 Data Capture 39
- 3.3.7 External Macros 40
- 3.4 Analysis Panel 41
- 3.4.1 Test Select 42
- 3.4.2 Statistics 43
- 3.4.3 Plot Enable 43
- 44 DS612RD2 44
- 3.5 Control Panel 45
- 3.5.1 DF Registers 46
- 3.5.2 DF Commands 46
- 3.5.3 SPI 46
- 3.5.4 Macros 47
- 3.5.5 GPIO 47
- 3.5.6 Customize 48
- 3.5.7 External Macros 48
- 4. BILL OF MATERIALS 49
- 50 DS612RD2 50
- 5. LAYER PLOTS 51
- 52 DS612RD2 52
- DS612RD2 53 53
- 54 DS612RD2 54
- DS612RD2 55 55
- 56 DS612RD2 56
- 6. SCHEMATICS 57
- 58 DS612RD2 58
- DS612RD2 59 59
- 60 DS612RD2 60
- DS612RD2 61 61
- 62 DS612RD2 62
- DS612RD2 63 63
- 64 DS612RD2 64
- DS612RD2 65 65
- 66 DS612RD2 66
- DS612RD2 67 67
- 68 DS612RD2 68
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