Cirrus-logic CS5460A User Manual Page 9
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CS5460A
DS487F5 9
SWITCHING CHARACTERISTICS
(T
A
= -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels:
Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF))
Notes: 24. Device parameters are specified with a 4.096 MHz clock, yet, clocks between 3 MHz to 20 MHz can be
used. However, for input frequencies over 5 MHz, an external oscillator must be used.
25. If external MCLK is used, then duty cycle must be between 45% and 55% to maintain this specification.
26. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
Parameter Symbol Min Typ Max Unit
Master Clock FrequencyCrystal/Internal Gate Oscillator (Note 24) MCLK 2.5 4.096 20 MHz
Master Clock Duty Cycle 40 - 60 %
CPUCLK Duty Cycle (Note 25) 40 60 %
Rise Times Any Digital Input Except SCLK (Note 26)
SCLK
Any Digital Output
t
rise
-
-
-
-
-
50
1.0
100
-
µs
µs
ns
Fall Times Any Digital Input Except SCLK (Note 26)
SCLK
Any Digital Output
t
fall
-
-
-
-
-
50
1.0
100
-
µs
µs
ns
Start-up
Oscillator Start-Up Time XTAL = 4.096 MHz (Note 27) t
ost
-60-ms
Serial Port Timing
Serial Clock Frequency SCLK - - 2 MHz
Serial Clock Pulse Width High
Pulse Width Low
t
1
t
2
200
200
-
-
-
-
ns
ns
SDI Timing
CS
Falling to SCLK Rising t
3
50 - - ns
Data Set-up Time Prior to SCLK Rising t
4
50 - - ns
Data Hold Time After SCLK Rising t
5
100 - - ns
SCLK Falling Prior to CS
Disable t
6
100 - - ns
SDO Timing
CS Falling to SDI Driving t
7
-2050ns
SCLK Falling to New Data Bit t
8
-2050ns
CS
Rising to SDO Hi-Z t
9
-2050ns
Auto-boot Timing
Serial Clock Pulse Width High
Pulse Width Low
t
10
t
11
8
8
MCLK
MCLK
MODE setup time to RESET
Rising t
12
50 ns
RESET
rising to CS falling t
13
48 MCLK
CS
falling to SCLK rising t
14
100 8 MCLK
SCLK falling to CS
rising t
15
16 MCLK
CS
rising to driving MODE low (to end auto-boot sequence). t
16
50 ns
SDO guaranteed setup time to SCLK rising t
17
100 ns
- Features 1
- Description 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 4
- LIST OF TABLES 4
- ANALOG CHARACTERISTICS 5
- 5V DIGITAL CHARACTERISTICS 7
- 3.3 V DIGITAL CHARACTERISTICS 8
- ABSOLUTE MAXIMUM RATINGS 8
- SWITCHING CHARACTERISTICS 9
- 10 DS487F5 10
- DS487F5 11 11
- 12 DS487F5 12
- 2.2 Performing Measurements 13
- Gain (dB) 14
- Configurations 16
- (just like voltage input) 17
- NOTE: Current channel 17
- 18 DS487F5 18
- DS487F5 19 19
- 20 DS487F5 20
- 3. FUNCTIONAL DESCRIPTION 21
- 3.1 Pulse-Rate Output 21
- Counter Format 22
- 3.2.1 Normal Format 22
- DS487F5 23 23
- Connector to 24
- Calibrator 24
- DS487F5 25 25
- 26 DS487F5 26
- DS487F5 27 27
- ±250 mV on both input 27
- ±50 mV.) 27
- 3.8.3 Calibration Sequence 28
- DS487F5 29 29
- (DC or AC) 30
- 3.9 Phase Compensation 31
- 3.11 Power Offset Register 32
- DS487F5 33 33
- 3.13 Input Filtering 34
- DS487F5 35 35
- 36 DS487F5 36
- DS487F5 37 37
- 3.15 Improving RFI Immunity 38
- 3.16 PCB Layout 38
- 4. SERIAL PORT OVERVIEW 38
- 4.1 Commands (Write Only) 39
- 4.1.1 Start Conversions 39
- 4.1.2 SYNC0 Command 39
- 4.1.3 SYNC1 Command 39
- 4.1.4 Power-Up/Halt 39
- 4.1.5 Power-Down 40
- 4.1.6 Calibration 40
- 4.1.7 Register Read/Write 41
- 4.2 Serial Port Interface 42
- 4.3 Serial Read and Write 42
- 4.3.1 Register Write 42
- 4.3.2 Register Read 42
- 4.4 System Initialization 42
- 4.6 CS5460A Power States 43
- 5. REGISTER DESCRIPTIONS 44
- 5.4 Cycle Count Register 46
- 5.9 Power Offset Register 48
- 5.12 Control Register 50
- 6. PIN DESCRIPTIONS 51
- 24L SSOP PACKAGE DRAWING 53
- 8. ORDERING INFORMATION 54
- 10. REVISION HISTORY 54
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