Cirrus-logic CS5460A User Manual download pdf (Page 23)

CS5460A

DS487F5 23

sented by one pulse, the CS5460A will issue a

“burst” of one or more pulses on EOUT

(and also

possibly on EDIR

). The CS5460A will issue as

many pulses as are necessary to reduce the run-

ning energy accumulation value in this register to a

value that is less than the energy represented in

one pulse. If the amount of energy that has been

registered over the most recent sampling period is

large enough that it cannot be expressed with only

one pulse, then a burst of pulses will be issued,

possibly followed by a period of time during which

there will be no pulses, until the next A/D sampling

period occurs. After the pulse or pulses are issued,

a certain residual amount of energy may be left

over in this internal energy accumulation register,

which is always less (in magnitude) than the

amount of energy represented by one pulse. In this

situation, the residual energy is not lost or discard-

ed, but rather it is maintained and added to the en-

ergy that is accumulated during the next A/D

conversion cycle. The amount of residual energy

that can be left over becomes larger as the

Pulse-Rate Register is set to lower and lower val-

ues, because lower Pulse-Rate Register values

correspond to a higher amount of energy per pulse

(for a given calibration).

3.2.2 Mechanical Counter Format

Setting the MECH bit in the Control Register to ‘1’

and the STEP bit to ‘0’ enables wide-stepping puls-

es for mechanical counters and similar discrete

counter instruments. In this format, active-low puls-

es are 128 ms wide when using a 4.096 MHz crys-

tal and K = 1. When energy is positive, the pulses

appear on EOUT

. When energy is negative, pulses

appear on EDIR

. To insure that pulses will not oc-

cur at a rate faster than the 128 ms pulse duration,

or faster than the mechanical counter can accom-

modate, the Pulse-Rate Register should be set to

an appropriate value. Because the duration of

each pulse is set to 128 ms, the maximum output

pulse frequency is limited to ~7.8 Hz (for

MCLK/K = 4.096 MHz). For values of MCLK / K

different than 4.096 MHz, the duration of one pulse

is (128 * 4.096 MHz) / (MCLK / K) milliseconds.

See Figure 11 for a diagram of the typical pulse

output.

3.2.3 Stepper Motor Format

Setting the STEP bit in the Control Register to ‘1’

and the MECH bit to ‘0’ transforms the EOUT

and

EDIR

pins into two stepper motor phase outputs.

When enough energy has been registered by the

CS5460A to register one positive/negative energy

EOUT

EDIR

Pulse-Rate Register Period

(MCLK / K)

for Integer n

Positive Energy Burst Negative Energy Burst

. . .

Figure 10. Time-plot representation of pulse output for a typical burst of pulses (Normal Format)

128 ms

EOUT

EDIR

Positive Energy

Negative Energy

...

Figure 11. Mechanical Counter Format on EOUT and EDIR

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 53 54

Comments to this Manuals

No comments

Cirrus-logic CS5460A User Manual Page 23

Comments to this Manuals

Related products and manuals for Hardware Cirrus-logic CS5460A