Cirrus-logic AN241 User Manual download pdf (Page 8)

AN241

4.4 Overview of Filter Topology #1

4.4.1 High Pass Filter and DC Biasing

The first stage of the buffer forms a high pass filter from the combination of the AC-coupling capacitor

along with the resistor that connects the positive terminal of the op-amp in the input signal path to the DC

bias voltage. The 3 dB corner of the high pass filter can be calculated as follows:

where:

is the value of the resistor (in Ohms)

is the value of the capacitor (in Farads)

In the input buffer shown in Figure 4,

= 100 k

Ω

and

= 1.0

F. This places the 3 dB corner at approx-

imately 1.59 Hz. Typically, this corner should be at least one decade below the bandwidth of interest in

order to prevent a significant droop in the frequency response.

Since the input impedance into the op-amp is extremely high, the effective input impedance into the ana-

log input buffer will be determined by the value of the resistors to the bias voltage in parallel with the

100 k

Ω

shunt resistors. In the input buffer shown above, the input impedance is approximately 50 k

Ω.

Ide-

ally, the larger this input impedance the better. However, in the input buffer shown in Figure 4, the AC-

coupling capacitor will initially be charged up via the op-amp connected to the on-chip voltage reference.

This charge up time is dependent on the size of the AC-coupling capacitor and the amount of series re-

sistance to the DC-biasing op-amp. The time constant can be calculated as follows:

where

= the amount of resistance between the AC-coupling capacitor and the DC-biasing op-amp (in

Ohms)

= the value of capacitance of the AC-coupling capacitor (in Farads)

In the input buffer shown in Figure 4,

=100 k

Ω

, and

= 1.0

F. This produces a time constant of 0.1 s.

This would indicate that the capacitor will charge up to within 99% of the final DC value in approximately

0.5 s (which is 5 time constants). The 100 k

Ω

resistors to ground on the input node allow a DC path to

charge the AC-coupling capacitors, regardless of whether or not there is an input signal source present.

4.4.2 Op Amp Circuitry and Anti-Aliasing Capacitor

The op-amp topology used in the input buffer shown in Figure 4 addresses two issues. First, it provides

an extremely low output impedance and therefore minimizes the amount of distortion presented to the

converters internal sampling circuits. By placing the 91

Ω

resistor in the feedback loop, it’s resistance is

divided by the open-loop gain of the op-amp, providing a sub-ohm output impedance. Secondly, this op-

amp topology provides a low pass filter. Using the recommended values, this filter remains flat throughout

the audio passband and provides approximately 2 0dB of rejection at the modulator sampling rate (where

the converter is susceptible to aliasing). The characteristics of this low pass filter can be changed by ad-

justing the values of the resistors and capacitors in the feedback loop. However, it is important to maintain

a flat frequency response throughout the passband of interest and to provide reasonable attenuation at

RC=

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