Cirrus-logic AN241 User Manual download pdf (Page 3)

AN241

where:

is the value of the resistor (in Ohms)

is the value of the capacitor (in Farads)

In the input buffer shown in Figure 2,

= 10 k

Ω

and

= 10

F. This places the 3 dB corner at approxi-

mately 1.59 Hz. Typically, this corner should be at least one decade below the bandwidth of interest in

order to prevent a significant droop in the frequency response.

The proper DC biasing (common mode level) is set via the on-chip reference (VQ or VCOM). In the input

buffer shown above, the bias is set through a 10k

Ω

resistor. Please note that this resistor value has sev-

eral implications. Since the input impedance into the op-amp is extremely high, the effective input imped-

ance into the analog input buffer will be determined by the value of the resistor to the bias voltage in

parallel with the 100 k

Ω

shunt resistor. In the input buffer shown above, the input impedance is approxi-

mately 9 k

Ω.

Ideally, the larger this input impedance the better. However, in the input buffer shown in Fig-

ure 2, the AC-coupling capacitor will initially be charged up via the on-chip reference (VQ or VCOM). This

charge up time is dependent on the size of the AC-coupling capacitor and the amount of series resistance

to the reference voltage supply. The reference pin (VQ or VCOM) has an associated output impedance

that must also be considered when calculating the charge up time. The time constant can be calculated

as follows:

where

= the amount of resistance between the AC-coupling capacitor and reference voltage (in

Ohms)

= the value of capacitance of the AC-coupling capacitor (in Farads)

In the input buffer shown in Figure 2,

= 35 k

Ω

(assuming a 25k

Ω

output impedance on the reference

pin), and

= 10

F. This produces a time constant of 0.35 s. This would indicate that the capacitor will

charge up to within 99% of the final DC value in approximately 1.75 s (which is 5 time constants). The

100 k

Ω

resistors to ground on the input node allow a DC path to charge the AC-coupling capacitors, re-

gardless of whether or not there is an input signal source present.

2.4.2 Op Amp Circuitry and Anti-Aliasing Capacitor

The op-amp topology used in the input buffer shown in Figure 2 addresses two issues. First, it provides

an extremely low output impedance and therefore minimizes the amount of distortion presented to the

converters internal sampling circuits. By placing the 91

Ω

resistor in the feedback loop, it’s resistance is

divided by the open-loop gain of the op-amp, providing a sub-ohm output impedance. Secondly, this op-

amp topology provides a low pass filter. Using the recommended values, this filter remains flat throughout

the audio passband and provides approximately 2 0dB of rejection at the modulator sampling rate (where

the converter is susceptible to aliasing). The characteristics of this low pass filter can be changed by ad-

justing the values of the resistors and capacitors in the feedback loop. However, it is important to maintain

a flat frequency response throughout the passband of interest and to provide reasonable attenuation at

the input sampling rate of the converter. Also, low value resistors should be used to minimize the addition

of resistor thermal noise.

RC=

1 2 3 4 5 6 7 8 ... 15 16

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