Cirrus-logic AN241 User Manual download pdf (Page 15)

AN241

In the input buffer shown in Figure 7,

≈

50 k

Ω

(100 k

Ω 

Ω

)

and

= 4.7

F. This places the 3 dB

corner at approximately 0.68 Hz. Typically, this corner should be at least one decade below the bandwidth

of interest in order to prevent a significant droop in the frequency response.

Since the input impedance into the op-amp is extremely high, the effective input impedance into the ana-

log input buffer will be determined by the parallel combination of the resistors in the divider in parallel with

the 10 0k

Ω

shunt resistor. In the input buffer shown above, the input impedance is approximately 33k

Ω.

Ideally, the larger this input impedance the better. However, in the input buffer shown in Figure 7, the AC-

coupling capacitor will initially be charged up via the resistor divider. This charge up time is dependent on

the size of the AC-coupling capacitor and the amount of resistance to the VA voltage supply. The time

constant can be calculated as follows:

where

= the amount of resistance between the AC-coupling capacitor and the voltage supply (in

Ohms)

= the value of capacitance of the AC-coupling capacitor (in Farads)

In the input buffer shown in Figure 7,

≈

50 k

Ω

(100 k

Ω 

Ω

), and

= 4.7

F. This produces a

time constant of approximately 0.24 s. This would indicate that the capacitor will charge up to within 99%

of the final DC value in approximately 1. 2s (which is 5 time constants). The 10 0k

Ω

resistors to ground

on the input nodes allow a DC path to charge the AC-coupling capacitor, regardless of whether or not

there is an input signal source present.

5.4.2 Op Amp Circuitry and Anti-Aliasing Capacitor

The op-amp topology used in the input buffer shown in Figure 7 addresses two issues. First, it provides

an extremely low output impedance and therefore minimizes the amount of distortion presented to the

converters internal sampling circuits. By placing the 91

Ω

resistor in the feedback loop, it’s resistance is

divided by the open-loop gain of the op-amp, providing a sub-ohm output impedance. Secondly, this op-

amp topology provides a low pass filter. Using the recommended values, this filter remains flat throughout

the audio passband and provides approximately 2 0dB of rejection at the modulator sampling rate (where

the converter is susceptible to aliasing). The characteristics of this low pass filter can be changed by ad-

justing the values of the resistors and capacitors in the feedback loop. However, it is important to maintain

a flat frequency response throughout the passband of interest and to provide reasonable attenuation at

the input sampling rate of the converter. Also, low value resistors should be used to minimize the addition

of resistor thermal noise.

Figure 7 implements a capacitor from the analog input to ground on each channel of the converter. This

capacitor is commonly referred to as the anti-aliasing capacitor, and performs several functions. The value

of the capacitor affects the overall low pass filter response and the amount of attenuation at the modulator

sampling rate. This capacitor also acts as a charge reservoir for the internal sampling capacitors. Since

this capacitor is located in the signal path, it is very important not to use capacitors with a large voltage

coefficient (such as general purpose ceramics) since they can degrade signal linearity.

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