Cirrus-logic CS43L21 User Manual

Copyright  Cirrus Logic, Inc. 2013 (All Rights Reserved)http://www.cirrus.comDS723F1JAN ‘13Low-Power, Stereo Digital-to-Analog ConverterFEATURES 98

10 DS723F1CS43L21+1.8V or +2.5V1 µFVQFILT+0.1 µF1 µFDGNDVL0.1 µF+1.8V, 2.5 Vor +3.3VI²S/LJMCLKDIV2RESETLRCKAGNDDEMMCLKSCLK0.1 µFVA_HPVD SDINCS43L211 µ

DS723F1 11CS43L213. CHARACTERISTIC AND SPECIFICATION TABLES(All Min/Max characteristics and specifications are guaranteed over the Specified Operating

12 DS723F1CS43L21ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)(Test conditions (unless otherwise specified): Input test signal is a full-scale 997

DS723F1 13CS43L21ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)(Test conditions (unless otherwise specified): Input test signal is a full-scale 997

14 DS723F1CS43L21LINE OUTPUT VOLTAGE CHARACTERISTICSTest conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave;

DS723F1 15CS43L21HEADPHONE OUTPUT POWER CHARACTERISTICSTest conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wav

16 DS723F1CS43L21COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Notes:8. Response is clock dependent and will scale with Fs. Note tha

DS723F1 17CS43L2110. After powering up the CS43L21, RESET should be held low after the power supplies and clocks aresettled.11. See “Example System C

18 DS723F1CS43L21SWITCHING SPECIFICATIONS - I²C CONTROL PORT(Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF)14. Data must be held for sufficient ti

DS723F1 19CS43L21SWITCHING CHARACTERISTICS - SPI CONTROL PORT(Inputs: Logic 0 = DGND, Logic 1 = VL)15. Data must be held for sufficient time to bridge

2 DS723F1CS43L21GENERAL DESCRIPTIONThe CS43L21 is a highly integrated, 24-bit, 96 kHz, low power stereo DAC. Based on multi-bit, delta-sigma modu-lati

20 DS723F1CS43L21DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) 17. The DC current draw represents the allowed curr

DS723F1 21CS43L21POWER CONSUMPTIONSee (Note 20)20. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate =4

22 DS723F1CS43L214. APPLICATIONS4.1 Overview4.1.1 ArchitectureThe CS43L21 is a highly integrated, low power, 24-bit audio D/A comprised of stereo digi

DS723F1 23CS43L214.2 Hardware Mode A limited feature-set is available when the D/A powers up in Hardware Mode (see “Recommended Power-Up Sequence” sec

24 DS723F1CS43L214.3 Analog OutputsAOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing optionsare available,

DS723F1 25CS43L214.3.2 Volume ControlsTwo digital volume control functions offer independent control of the SDIN signal path into the mixer aswell as

26 DS723F1CS43L214.3.5 Tone ControlShelving filters are used to implement bass and treble (boost and cut) with four selectable corner frequen-cies. Bo

DS723F1 27CS43L214.3.7 Line-Level Outputs and FilteringThe device contains on-chip buffer amplifiers capable of producing line level single-ended outp

28 DS723F1CS43L214.3.8 On-Chip Charge PumpAn on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dualrail suppl

DS723F1 29CS43L214.4.1 SlaveLRCK and SCLK are inputs in Slave Mode. The speed of the D/A is automatically determined based onthe input MCLK/LRCK ratio

DS723F1 3CS43L21TABLE OF CONTENTS1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE ... 61.

30 DS723F1CS43L214.4.3 High-Impedance Digital OutputThe serial port may be placed on a clock/data bus that allows multiple masters for the SCLK/LRCK I

DS723F1 31CS43L21 4.6 InitializationThe initialization and Power-Down sequence flowchart is shown in Figure 16 on page 31. The device entersa Power-Do

32 DS723F1CS43L214.8 Recommended Power-Down SequenceTo minimize audible pops when turning off or placing the device in standby,1. Mute the DACs. 2. Di

DS723F1 33CS43L21InitializationSoftware ModeRegisters setup to desired settings.RESET = Low?No Power1. No audio signal generated.Off Mode (Power Appli

34 DS723F1CS43L214.9 Software ModeThe control port is used to access the registers allowing the D/A to be configured for the desired operationalmodes

DS723F1 35CS43L21operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows

36 DS723F1CS43L214.9.3 Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to

DS723F1 37CS43L215. REGISTER QUICK REFERENCE Software mode register defaults are as shown. “Reserved” registers must maintain their default state.Addr

38 DS723F1CS43L2110h Vol. Control PCMMIXAMUTE_PCMMIXAPCMMIXAVOL6PCMMIXA VOL5PCMMIXA VOL4PCMMIXA VOL3PCMMIXA VOL2PCMMIXA VOL1PCMMIXAVOL0p45default1 000

DS723F1 39CS43L211Dh Reserved Reserved ReservedReserved Reserved Reserved Reserved Reserved Reserveddefault0 01111111Eh ReservedReserved Reserved Rese

4 DS723F1CS43L216.2 Power Control 1 (Address 02h) ...

40 DS723F1CS43L216. REGISTER DESCRIPTIONAll registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register whic

DS723F1 41CS43L21Function:The entire D/A will enter a low-power state when this function is enabled. The contents of the control portregisters are ret

42 DS723F1CS43L216.4 Interface Control (Address 04h)Master/Slave Mode (M/S)Default: 00 - Slave1 - MasterFunction:Selects either master or slave operat

DS723F1 43CS43L21These bits select the gain multiplier for the headphone/line outputs. See “Line Output Voltage Characteris-tics” on page 14 and “Head

44 DS723F1CS43L21This function will freeze the previous settings of, and allow modifications to be made to all control port reg-isters without the cha

DS723F1 45CS43L21Soft RampSoft Ramp allows level changes, either by gain changes, attenuation changes or muting, to be implementedby incrementally ram

46 DS723F1CS43L216.8 Beep Frequency & Timing Configuration (Address 12h)Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable func

DS723F1 47CS43L21Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register.Beep Off Time (OFFTIME[2:0])

48 DS723F1CS43L216.10 Beep Configuration & Tone Configuration (Address 14h)Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable f

DS723F1 49CS43L21Tone Control Enable (TC_EN) Default = 00 - Disabled1 - EnabledFunction:The Bass and Treble tone control features are active when this

DS723F1 5CS43L21Figure 18.Control Port Timing in SPI Mode ...

50 DS723F1CS43L21AOUTA (Address 16h) & AOUTB (Address 17h)Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control i

DS723F1 51CS43L216.14 Limiter Threshold SZC Disable (Address 19h)Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function contro

52 DS723F1CS43L21Limiter Soft Ramp Disable (LIM_SRDIS) Default: 00 - Off1 - OnFunction:Overrides the DAC_SZC setting. When this bit is set, the Limite

DS723F1 53CS43L21Limiter RELEASE Rate (RRATE[5:0]) Default: 111111 Function:Sets the rate at which the limiter releases the digital attenuation from

54 DS723F1CS43L21Signal Processing Engine Overflow (SPEX_OVFL)Default: 0Function:Indicates a digital overflow condition within the data path after the

DS723F1 55CS43L217. ANALOG PERFORMANCE PLOTS7.1 Headphone THD+N versus Output Power PlotsTest conditions (unless otherwise specified): Input test sign

56 DS723F1CS43L21 G = 0.6047G = 0.7099G = 0.8399G = 1.0000G = 1.1430Legend-100-20-95-90-85-80-75-70-65-60-55-50-45-40-35-30dBr A0 60m6m 12m 18m 24

DS723F1 57CS43L217.2 Headphone Amplifier EfficiencyThe architecture of the headphone amplifier is that of typical class AB amplifiers. Test conditions

58 DS723F1CS43L218. EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled*The”MCLKDIV2” pin 4 must be set HI.Sample RateLRCK (kHz)MCLK (MHz)1024x 1

DS723F1 59CS43L218.2 Auto Detect Disabled Sample RateLRCK (kHz)MCLK (MHz)512x 768x 1024x 1536x 2048x 3072x8 - 6.1440 8.1920 12.2880 16.3840 24.576011.

6 DS723F1CS43L211. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE Pin Name # Pin DescriptionLRCK1Left Right Clock (Input/Output) - Determines

60 DS723F1CS43L219. PCB LAYOUT CONSIDERATIONS9.1 Power Supply, GroundingAs with any high-resolution converter, the CS43L21 requires careful attention

DS723F1 61CS43L2110.DIGITAL FILTERSFigure 27. Passband Ripple Figure 28. StopbandFigure 29. Transition Band Figure 30. Transition Band (Detail)

62 DS723F1CS43L2111.PARAMETER DEFINITIONSDynamic RangeThe ratio of the rms value of the signal to the rms sum of all other spectral components over th

DS723F1 63CS43L2113.PACKAGE DIMENSIONS 1. Dimensioning and tolerance per ASME Y 14.5M-1995.2. Dimensioning lead width applies to the plated termin

64 DS723F1CS43L2114.ORDERING INFORMATION 15.REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order #CS43L21Low-Power St

DS723F1 7CS43L21AOUTBAOUTA1011Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris-tics specification

8 DS723F1CS43L211.1 Digital I/O Pin CharacteristicsThe logic level for each input should not exceed the maximum ratings for the VL power supply. Pin N

DS723F1 9CS43L212. TYPICAL CONNECTION DIAGRAMS 1 µF+1.8 V or +2.5 V1 µFVQFILT+0.1 µF1 µFDGNDVL0.1 µF+1.8 V, +2.5 Vor +3.3 VSCL/CCLKSDA/CDINRESET2