Cirrus-logic CS5364 User Manual Page 26
- Page / 42
- Table of contents
- BOOKMARKS
- Features 1
- Description 2
- TABLE OF CONTENTS 3
- LIST OF FIGURES 4
- LIST OF TABLES 5
- 1. PIN DESCRIPTION 6
- DS625F5 7 7
- 8 DS625F5 8
- Stand-Alone Mode 8
- Control Port Mode 8
- DS625F5 9 9
- ABSOLUTE RATINGS 10
- SYSTEM CLOCKING 10
- DC POWER 11
- LOGIC LEVELS 11
- 100 - ppm/°C 12
- OVERFLOW TIMEOUT 14
- 4. APPLICATIONS 19
- 4.3 Master Clock Source 20
- SCLK & LRCK/FS 21
- 4.5.1 I²S and LJ Format 22
- 4.5.2 TDM Format 23
- 4.6 Speed Modes 23
- 4.6.1 Sample Rate Ranges 23
- MCLK DIVIDERS 24
- SAMPLE RATE DIVIDERS 24
- 26 DS625F5 26
- TDM MASTER DSM Fs = 96 kHz 26
- TDM SLAVE DSM Fs = 96 kHz 26
- TDM MASTER QSM Fs = 192 kHz 26
- TDM SLAVE QSM Fs = 192 kHz 26
- 4.8 Reset 27
- 4.8.1 Power-Down Mode 27
- 4.9 Overflow Detection 27
- 4.10 Analog Connections 28
- 4.12 DC Offset Control 29
- 4.13 Control Port Operation 30
- 4.13.1 SPI Mode 30
- 4.13.2 I²C Mode 31
- 5. REGISTER MAP 32
- 5.7 05h Reserved 34
- 5.9 07h Reserved 34
- 5.11 09h Reserved 35
- 6. FILTER PLOTS 36
- DS625F5 37 37
- 38 DS625F5 38
- 7. PARAMETER DEFINITIONS 39
- 8. PACKAGE DIMENSIONS 40
- THERMAL CHARACTERISTICS 40
- 48L LQFP PACKAGE DRAWING 40
- 9. ORDERING INFORMATION 41
- 10.REVISION HISTORY 41
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