Cirrus-logic CS4953xx User Manual download pdf (Page 13)

CS4953xx Data Sheet

32-bit Audio Decoder DSP Family

DS705F2 13

5.9 Switching Characteristics — Internal Clock

Parameter Symbol Min Max Unit

Internal DCLK frequency

1. After initial power-on reset, F

dclk

= F

xtal

. After initial kick-start commands, the PLL is locked to max F

dclk

and remains

locked until the next power-on reset.

dclk

—130MHz

CS49530x-CVZ

CS49531x-CQZ

CS49531x-CVZ

CS49530x-DVZ

CS49531x-DVZ

—F

xtal

150

131

—

Internal DCLK period

DCLKP — 7.7 ns

CS49530x-CVZ

CS49531x-CQZ

CS49531x-CVZ

CS49530x-DVZ

CS49531x-DVZ

—6.7

6.7

7.63

1/F

xtal

1/F

xtal

1/F

xtal

1/F

xtal

1/F

xtal

—

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 36 37

CS4953xx Data Sheet 1
Table of Contents 2
List of Figures 3
List of Tables 3
1 Documentation Strategy 4
2 Overview 4
3 Code Overlays 5
4.1 Coyote 32-bit DSP Core 7
4.2 On-chip DSP Peripherals 8
4.3 DSP I/O Description 8
5.1 Absolute Maximum Ratings 9
DS705F2 15 15
SCP_MISO 16
SCP_MOSI 16
C Slave Mode 17
C Master Mode 18
DS705F2 20 20
DS705F2 22 22
DAI_SCLK 23
DAI_DATAn 23
DAO_SCLK 25
DAO_LRCLK 25
DS705F2 26 26
DS705F2 27 27
6 Ordering Information 28
8 Device Pinout Diagrams 30
128-pin LQFP 31
(CS495304/CS495314) 31
144-pin LQFP 32
(CS495313) 32
10 Revision History 35
April, 2011 36
August, 2011 36
February, 2012 36
Revision Date Changes 36
DS705F2 37 37

Comments to this Manuals

No comments

Cirrus-logic CS4953xx User Manual Page 13

Comments to this Manuals

Related products and manuals for Hardware Cirrus-logic CS4953xx