Cirrus-logic CS4271 User Manual download pdf (Page 36)

CS4271

36 DS592F1

6.2 I²C Mode

I²C

mode, SDA is a bi-directional data line. Data is clocked into and out of the part by the clock, SCL, with the clock

to data relationship as shown in Figure 18. There is no CS

pin. Pin AD0 forms the partial chip address and should be

tied to VA or AGND as required. The upper 6 bits of the 7-bit address field must be 001000. To communicate with the

CS4271

the LSB of the chip address field, which is the first byte sent to the CS4271, should match the setting of the

AD0 pin. The eighth bit of the address byte is the R/W

bit (high for a read, low for a write). If the operation is a write,

the next byte is the Memory Address Pointer, MAP, which selects the register to be read or written. The MAP is then

followed by the data to be written. If the operation is a read, then the contents of the register pointed to by the MAP will

be output after the chip address.

The CS4271 has MAP auto increment capability, enabled by the INCR bit in the MAP. If INCR is 0, then the MAP

will stay constant for successive writes. If INCR is set, then MAP will auto increment after each byte is written, al-

lowing block reads or writes of successive registers.

Table 10. Memory Address Pointer (MAP)

76543210

INCR Reserved Reserved Reserved MAP3 MAP2 MAP1 MAP0

00000000

INCR - Auto MAP Increment Enable

Default = ‘0’.

0 - Disabled

1 - Enabled

MAP(3:0) - Memory Address Pointer

Default = ‘0000’.

SDA

SCL

001000

ADDR

AD0

R/W

Start

ACK

DATA

1-8

ACK

DATA

1-8

ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Note 1

Figure 18. Control Port Timing, I²C Mode

1 2 ... 31 32 33 34 35 36 37 38 39 40 41 ... 52 53

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Cirrus-logic CS4271 User Manual Page 36

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