Cirrus-logic CS2300-01 User Manual download pdf

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Advance Product Information

This document contains information for a new product.

Cirrus Logic reserves the right to modify this product without notice.

1x, 2x, 4x, and 8x Clock Multiplier with Internal LCO

Features

 Clock Multiplier / Jitter Reduction

– Generates a Low Jitter 6 - 75 MHz Clock

from a Jittery 750 kHz to 30 MHz Clock

Source

 Internal LCO Reference Clock

 1 Hz Loop Filter Bandwidth

 Selectable Multiplication Factors

– 1x, 2x, 4x, and 8x

 Output Enable Pin

 Lock Indicator

 Minimal Board Space Required

– No External Analog Loop-filter

Components

General Description

The CS2300-01 is an extremely versatile system clock-

ing device that utilizes a programmable phase lock loop.

The CS2300-01 is based on a hybrid analog-digital PLL

architecture comprised of a unique combination of a

Delta-Sigma Fractional-N Frequency Synthesizer and a

Digital PLL. This architecture allows for generation of a

low-jitter clock relative to an external noisy synchroniza-

tion clock with frequencies as low as 750 kHz. The

CS2300-01 is a CS2300-OTP device that has been pre-

configured at the factory. There are three hardware con-

figuration pins available for mode and feature selection.

Ordering Information

The CS2300-01 is available in a 10-pin MSOP package

in Commercial (-10°C to +70°C) grade. Customer de-

velopment kits are also available for custom device

prototyping and device evaluation. Please see “Order-

ing Information” on page 2 for complete details.

Pin-Out Diagram

Hardware Controls Settings

FILTP

CLK_OUT

GND

FILTN

OUT_EN

LOCK

CLK_IN

M1 M0 PLL_OUT

1x CLK_IN

01 2x CLK_IN

10 4x CLK_IN

11 8x CLK_IN

OUT_EN CLK_OUT

Enabled

1 High Impedance

6 MHz to 75 MHz

PLL Output

3.3 V

Fractional-N

Frequency Synthesizer

1 Hz BW Digital PLL &

Fractional N Logic

Output to Input

Clock Ratio

750 kHz to 30 MHz

Frequency Reference

LCO

M[1:0]

00=1x

01=2x

10=4x

11=8x

Ratio Selection

PLL Lock

Indicator

Output

Enable/Disable

FILTP

FILTN

0.1 µF

CLK_IN

OUT_EN

LOCK

0.1 µF 1 µF

GND

CLK_OUT

AUG '08

PS846A4

CS2300-01

1 2 3

CS2300-01 1
6. REVISION HISTORY 3

Summary of Contents

Page 1 - CS2300-01

Page 2

CS2300-01PS846A4 21. PIN DESCRIPTIONS See the CS2300-OTP datasheet for additional pin de-scription information.2. SPECIFICATIONSPlease see the CS2300-

Page 3 - 6. REVISION HISTORY

CS2300-01PS846A4 36. REVISION HISTORYRelease ChangesA1 Initial ReleaseA2 Corrected part numberA3 Reduced page count and updated formattingA4 Updated f

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